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Volumn , Issue , 2009, Pages 85-88

Migrating from Planar to FinFET for further CMOS scaling: SOI or bulk?

Author keywords

[No Author keywords available]

Indexed keywords

BULK SUBSTRATES; CMOS SCALING; FIGURES OF MERITS; FINFETS; INTRINSIC DEVICE; JUNCTION CAPACITANCES; PARASITICS; RING OSCILLATOR; SRAM CELL; VOLTAGE GAIN;

EID: 72849127601     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2009.5331587     Document Type: Conference Paper
Times cited : (20)

References (8)
  • 1
    • 72849140007 scopus 로고    scopus 로고
    • B. Parvais et al, The device architecture dilemma for cmos technologies: opportunities & challenges of finFET over planar MOSFET, VLSI-TSA 2009, (in press).
    • B. Parvais et al, "The device architecture dilemma for cmos technologies: opportunities & challenges of finFET over planar MOSFET", VLSI-TSA 2009, (in press).
  • 2
    • 38649140309 scopus 로고    scopus 로고
    • Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography
    • M. van Dal et al, "Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography", VLSI 2007, pp, 110-111.
    • (2007) VLSI , pp. 110-111
    • van Dal, M.1
  • 3
    • 84888460734 scopus 로고    scopus 로고
    • The International Technology Roadmap for Semiconductors ITRS
    • The International Technology Roadmap for Semiconductors (ITRS), 2008, http://www.itrs.net/ .
    • (2008)
  • 4
    • 51949085647 scopus 로고    scopus 로고
    • Flexible and Robust Capping-Metal Gate Integration Technology enabling multiple-VT CMOS in MuGFETs
    • A. Veloso et al, "Flexible and Robust Capping-Metal Gate Integration Technology enabling multiple-VT CMOS in MuGFETs", VLSI 2008, pp. 14-15.
    • (2008) VLSI , pp. 14-15
    • Veloso, A.1
  • 5
    • 52349118774 scopus 로고    scopus 로고
    • Strain enhanced Low-VT CMOS featuring La/AI-doped HfSiO/TaC and 10ps Inverter Delay
    • S. Kubicek et al, "Strain enhanced Low-VT CMOS featuring La/AI-doped HfSiO/TaC and 10ps Inverter Delay, VLSI 2008, pp.130-131.
    • (2008) VLSI , pp. 130-131
    • Kubicek, S.1
  • 6
    • 51849135409 scopus 로고    scopus 로고
    • Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length
    • N. Collaert et aI, "Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length", ICICDT 2008, pp. 59-62.
    • (2008) ICICDT , pp. 59-62
    • Collaert, N.1    aI2
  • 7
    • 51949118252 scopus 로고    scopus 로고
    • FinFET Performance Advantage at 22nm: An AC perspective
    • M. Guillorn et aI, "FinFET Performance Advantage at 22nm: An AC perspective", VLSI 2008, pp. 12-13.
    • (2008) VLSI , pp. 12-13
    • Guillorn, M.1    aI2
  • 8
    • 0033314624 scopus 로고    scopus 로고
    • Self-heating characterization for SOl MOSFET based on AC output conductance
    • W. Jin et al, "Self-heating characterization for SOl MOSFET based on AC output conductance" , IEDM 1999, pp. 175-178.
    • (1999) IEDM , pp. 175-178
    • Jin, W.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.