The device architecture dilemma for CMOS technologies: Opportunities & challenges of FinFet over planar MOSFET

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 2009, Pages 80-81

  Parvais, B ^a   Mercha, A ^a   Collaert, N ^a   Rooyackers, R ^a   Ferain, I ^a   Jurczak, M ^a   Subramanian, V ^a   De Keersgieter, A ^a   Chiarella, T ^a   Kerner, C ^a   Witters, L ^a   Biesemans, S ^a   Hoffman, T ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY; COMPARATIVE ANALYSIS; DEVICE ARCHITECTURES; FINFETS; INVERTOR; MIXED SIGNAL; MOS-FET; MOSFETS; PLANAR DEVICES; SHORT-CHANNEL EFFECT; SPEED SENSITIVITY; VOLTAGE GAIN;

SECURITY SYSTEMS; TECHNOLOGY;

MOSFET DEVICES;

EID: 72849140007     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2009.5159300     Document Type: Conference Paper

References (7)

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2. S. Kubicek et al., Proc. IEDM, 2007, pp. 49-52, Dec. 2007;
3. C. Gustin et al., Proc. VLSI-TSA, 2007. pp. 168-169, April 2007;
4. N. Collaert et al., ICICDT 2008, pp. 59-62, June 2008;
5. J. Johnson et al., IEEE Electr. Dev. Let., July 2008, pp. 802-804;
6. B. Parvais et al., IEEE SOI Conf. 2007, paper 3-5, Oct. 2007;
7. W. Wu et al., IEEE Trans. Electr. Dev, April 2007, pp. 692-698.