-
1
-
-
0034451272
-
Characterization of single-event upsets in a flash analog-to-digital converter (AD9058)
-
S. Buchner, T. Meehan, A. Campbell, K. Clark, and D. McMorrow, "Characterization of single-event upsets in a flash analog-to-digital converter (AD9058)," IEEE Trans. Nucl. Sci., vol. 47, pp. 2358-2364, 2000.
-
(2000)
IEEE Trans. Nucl. Sci.
, vol.47
, pp. 2358-2364
-
-
Buchner, S.1
Meehan, T.2
Campbell, A.3
Clark, K.4
McMorrow, D.5
-
2
-
-
72349093678
-
-
Online
-
CREME96, [Online]. Available: https://creme96.nrl.navy.mil/
-
-
-
-
4
-
-
34447290679
-
Experimental and TCAD investigation of the two components of the impact ionization MOSFET (IMOS) switching
-
F. Mayer, C. Le Royer, G. Le Carval, L. Clavelier, and S. Deleonibus, "Experimental and TCAD investigation of the two components of the impact ionization MOSFET (IMOS) switching," IEEE Electron Device Lett., vol. 28, pp. 619-621, 2007.
-
(2007)
IEEE Electron Device Lett.
, vol.28
, pp. 619-621
-
-
Mayer, F.1
Le Royer, C.2
Le Carval, G.3
Clavelier, L.4
Deleonibus, S.5
-
5
-
-
62349084030
-
A full TCAD simulation and 3D parasitic capacitances extraction in 90 nm NAND flash memories
-
J. Postel-Pellerin, P. Canet, F. Lalande, R. Bouchakour, F. Jeuland, B. Bertello, and B. Villard, "A full TCAD simulation and 3D parasitic capacitances extraction in 90 nm NAND flash memories," in Proc. 9th Annu. Non-Volatile Memory Technology Symp., 2008, pp. 1-4.
-
(2008)
Proc. 9th Annu. Non-Volatile Memory Technology Symp.
, pp. 1-4
-
-
Postel-Pellerin, J.1
Canet, P.2
Lalande, F.3
Bouchakour, R.4
Jeuland, F.5
Bertello, B.6
Villard, B.7
-
6
-
-
0038721289
-
Basic mechanisms and modeling of single-event upset in digital microelectronics
-
P. Dodd and L. Massengill, "Basic mechanisms and modeling of single-event upset in digital microelectronics," IEEE Trans. Nucl. Sci., vol. 50, pp. 583-602, 2003.
-
(2003)
IEEE Trans. Nucl. Sci.
, vol.50
, pp. 583-602
-
-
Dodd, P.1
Massengill, L.2
-
7
-
-
51349109765
-
Efficient modeling of single event transients directly in compact device models
-
A. M. Francis, M. Turowski, J. Holmes, and H. Mantooth, "Efficient modeling of single event transients directly in compact device models," in IEEE Int. Behavioral Modeling and Simulation Workshop, 2007, pp. 73-77.
-
(2007)
IEEE Int. Behavioral Modeling and Simulation Workshop
, pp. 73-77
-
-
Francis, A.M.1
Turowski, M.2
Holmes, J.3
Mantooth, H.4
-
9
-
-
33144489763
-
Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design
-
B. Olson, D. Ball, K. Warren, L. Massengill, N. Haddad, S. Doyle, and D. McMorrow, "Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design," IEEETrans. Nucl. Sci., vol. 52, pp. 2132-2136, 2005.
-
(2005)
IEEE Trans. Nucl. Sci.
, vol.52
, pp. 2132-2136
-
-
Olson, B.1
Ball, D.2
Warren, K.3
Massengill, L.4
Haddad, N.5
Doyle, S.6
McMorrow, D.7
-
10
-
-
0036947787
-
Monte Carlo exploration of neutron-induced SEU-sensitive volumes in SRAMs
-
J. Palau, R. Wrobel, K. Castellani-Coulie, M. Calvet, P. Dodd, and F. Sexton, "Monte Carlo exploration of neutron-induced SEU-sensitive volumes in SRAMs," IEEE Trans. Nucl. Sci., vol. 49, pp. 3075-3081, 2002.
-
(2002)
IEEE Trans. Nucl. Sci.
, vol.49
, pp. 3075-3081
-
-
Palau, J.1
Wrobel, R.2
Castellani-Coulie, K.3
Calvet, M.4
Dodd, P.5
Sexton, F.6
-
11
-
-
33846326848
-
Single-event tolerant latch using cas- code-voltage switch logic gates
-
M. C. Casey, B. L. Bhuva, J. D. Black, L. W. Massengill, O. A. Amusan, and A. F. Witulski, "Single-event tolerant latch using cas- code-voltage switch logic gates," IEEE Trans. Nucl. Sci., vol. 53, pp. 3386-3391, 2006.
-
(2006)
IEEE Trans. Nucl. Sci.
, vol.53
, pp. 3386-3391
-
-
Casey, M.C.1
Bhuva, B.L.2
Black, J.D.3
Massengill, L.W.4
Amusan, O.A.5
Witulski, A.F.6
-
12
-
-
58849161337
-
Simulation study on the effect of multiple node charge collection on error cross-section in CMOS sequential logic
-
M. C. Casey, A. R. Duncan, B. L. Bhuva, W. H. Robinson, and L. W. Massengill, "Simulation study on the effect of multiple node charge collection on error cross-section in CMOS sequential logic," IEEE Trans. Nucl. Sci., vol. 55, pp. 3136-3140, 2008.
-
(2008)
IEEE Trans. Nucl. Sci.
, vol.55
, pp. 3136-3140
-
-
Casey, M.C.1
Duncan, A.R.2
Bhuva, B.L.3
Robinson, W.H.4
Massengill, L.W.5
-
14
-
-
80052736148
-
A bias dependent single-event model implemented into BSIM4 and a 90 nm CMOS process design kit
-
Quebec, Canada, Jul. 20-24
-
J. Kauppila, "A bias dependent single-event model implemented into BSIM4 and a 90 nm CMOS process design kit," presented at the NSREC 2009, Quebec, Canada, Jul. 20-24, 2009.
-
(2009)
NSREC 2009
-
-
Kauppila, J.1
-
15
-
-
0030375853
-
Upset hardened memory design for submicron CMOS technology
-
T. Calin, M. Nicolaidis, and R. Velazco, "Upset hardened memory design for submicron CMOS technology," IEEE Trans. Nucl. Sci., vol. 43, pp. 2874-2878, 1996.
-
(1996)
IEEE Trans. Nucl. Sci.
, vol.43
, pp. 2874-2878
-
-
Calin, T.1
Nicolaidis, M.2
Velazco, R.3
-
16
-
-
49349100285
-
Modeling and analysis method for radiatION-induced upsets in modern IC device models
-
A. M. Francis, D. Dimitrov, J. Holmes, and A. Mantooth, "Modeling and analysis method for radiatION-induced upsets in modern IC device models," in Proc. IEEE Aerospace Conf., 2008, pp. 1-10.
-
(2008)
Proc. IEEE Aerospace Conf.
, pp. 1-10
-
-
Francis, A.M.1
Dimitrov, D.2
Holmes, J.3
Mantooth, A.4
-
17
-
-
72349088531
-
-
ModLyng Integrated Modeling Environment: Modeling and User's Guide Lynguent, Inc., 2007
-
ModLyng Integrated Modeling Environment: Modeling and User's Guide Lynguent, Inc., 2007.
-
-
-
-
18
-
-
72349098217
-
-
General Purpose Layout Surveyor (GPLS) University of Arkansas, MSCAD Laboratory, Fayetteville
-
General Purpose Layout Surveyor (GPLS) University of Arkansas, MSCAD Laboratory, Fayetteville.
-
-
-
-
19
-
-
51549121360
-
Mitigation techniques for single event induced charge sharing in a 90 nm bulk CMOS process
-
O. Amusan, L. Massengill, M. Baze, B. Bhuva, A. Witulski, J. Black, A. Balasubramanian, M. Casey, D. Black, J. Ahlbin, R. Reed, and M. McCurdy, "Mitigation techniques for single event induced charge sharing in a 90 nm bulk CMOS process," in Proc. IEEE Int. Reliability Physics Symp., 2008, pp. 468-472.
-
(2008)
Proc. IEEE Int. Reliability Physics Symp.
, pp. 468-472
-
-
Amusan, O.1
Massengill, L.2
Baze, M.3
Bhuva, B.4
Witulski, A.5
Black, J.6
Balasubramanian, A.7
Casey, M.8
Black, D.9
Ahlbin, J.10
Reed, R.11
McCurdy, M.12
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