Single-event tolerant latch using cascode-voltage switch logic gates

IEEE Transactions on Nuclear Science

Volumn 53, Issue 6, 2006, Pages 3386-3391

  Casey, Megan C ^a,b   Bhuva, Bharat L ^a,b   Black, Jeff D ^a,b   Massengill, Lloyd W ^a,b   Amusan, Oluwole A ^a,b   Witulski, Arthur F ^a,b  

^a IEEE   (United States)

^b VANDERBILT UNIVERSITY   (United States)

Author keywords

CMOS; Digital circuits; Radiation hardening; Sequential circuits; Single event

Indexed keywords

CASCODE-VOLTAGE SWITCH LOGIC GATES; LATCH DESIGN; SINGLE EVENT TOLERANT;

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIGITAL CIRCUITS; RADIATION HARDENING; SEQUENTIAL CIRCUITS;

LOGIC GATES;

EID: 33846326848     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2006.884970     Document Type: Conference Paper

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