Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling

15th International Workshop on Thermal Investigations of ICs and Systems, THERMINIC 2009

Volumn , Issue , 2009, Pages 50-55

  Atienza, David ^a  

^a EPFL   (Switzerland)

Author keywords

2D 3D MPSoC; Active cooling; Close loop systems; FPGA emulation; Thermal modeling; Transient analysis

Indexed keywords

ACTIVE COOLING; CLOSE LOOP; CLOSE-LOOP SYSTEMS; CONSUMER ELECTRONICS MARKETS; CYCLE ACCURATE; DESIGN CONSTRAINTS; DYNAMIC FREQUENCY; EMULATED SYSTEMS; EMULATION SYSTEM; ENERGY CONSUMPTION; FAST TRANSIENTS; FINITE ELEMENT SIMULATIONS; FLOORPLANS; FPGA EMULATION; HARDWARE COMPONENTS; HOST COMPUTERS; KEY ELEMENTS; LIQUID COOLING; LIQUID FLOW; MULTIMEDIA APPLICATIONS; MULTIPLE APPLICATIONS; MULTIPROCESSOR-SYSTEM; NEW TENDENCIES; ON CHIPS; ORDINARY DIFFERENTIAL EQUATION SOLVER; RUNNING-IN; RUNTIMES; SOFTWARE-BASED; SPEED-UPS; STATE-OF-THE-ART METHODS; SYSTEM STATISTICS; SYSTEMS ON CHIPS; THERMAL MANAGEMENT; THERMAL MAPS; THERMAL MODEL; THERMAL MODELING; THERMAL RUNAWAYS; THERMAL SIMULATORS; THREE ORDERS OF MAGNITUDE; TIME-TO-MARKET; VOLTAGE-SCALING;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER HARDWARE; COMPUTER SOFTWARE; CONSUMER ELECTRONICS; COOLING; DESIGN; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LIQUIDS; MICROPROCESSOR CHIPS; MULTIMEDIA SYSTEMS; ORDINARY DIFFERENTIAL EQUATIONS; SIMULATORS; SOIL STRUCTURE INTERACTIONS; THERMOANALYSIS; THREE DIMENSIONAL; TRANSIENT ANALYSIS;

COOLING SYSTEMS;

EID: 71749102205     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (33)

1. D. Pham et al., Design and Implementation of a First-Generation Cell Processor., Proc. ISSCC, 2005.
2. P. Kongetira et al.,Niagara: A 32-way multithreaded SPARC processor., IEEE Micro, 2005.
3. Tilera Corporation, Tilera's 64-core architecture, 2008, www.tilera.com/products/processors.php
4. W. Davis, et al., Demystifying 3D ICs: The Pros and Cons of Going Vertical. IEEE Des&Test, 2005.
5. M. Healy, et al., Multiobjective microarchitectural floorplanning for 2D and 3D ICs. IEEE Transactions on CAD, 2007
6. K. Skadron et al., Temperature-aware microarchitecture: Modeling and implementation (Hot-spot simulator), IEEE TACO, 2004
7. G. Paci et al., Exploring temperature-aware design in low-power MPSoCs, Proc. DATE, 2006.
8. M.-N. Sabry, High-precision thermal models, IEEE TCPT, 2005.
9. Cadence Palladium II, 2005. http://www.cadence.com.
10. ARM integrator AP, 2004. http://www.arm.com.
11. Emulation Engineering. Zebu models, http://www.eve-team.com.
12. T. Brunschwiler et al., Direct liquid-jet impingement cooling with micron-sized nozzle array and distributed return architecture. Proc. ITHERM, 2006.
13. T. Brunschwiler, et al., Interlayer cooling potential in vertically integrated packages, Microsyst. Technologies, 2008.
14. F. Mulas et al., Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures, Proc. DATE, 2008.
15. D. Atienza, et al., A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip. Proc. DAC, 2006.
16. B. Richard, et al., Numerical Analysis, Brooks Cole, 2000.
17. A.K. Coskun, et al., Dynamic Thermal Management in 3D Multicore Architectures, Proc. DATE, 2009.
18. A. Jerraya, et al. Multiprocessor SoCs. Morgan Kaufmann, 2005.
19. G. Braun, et al. Processor/memory co-exploration on multiple abstraction levels. Proc. DATE, 2003.
20. P. S. Magnusson, et al. Simics: A full system simulation platform. IEEE Computer, 2002.
21. P. Paulin, et al. Stepnp: A system-level exploration platform for network processors, IEEE Des&Test , 2002.
22. Coware, Convergence and Lisatek product lines, 2006. http://www. coware.com
23. ARM, PrimeXSys platform architecture and methodologies, white paper, 2005, http://www.arm.com/
24. Heron Engineering, SoCemulation, 2004, http://www.hunteng.co.uk
25. M. D. Nava, et al., An open platform for developing MPSoC, IEEE Computer, 2005.
26. Y. Nakamura, A fast HW/SW co-verification method for SoC by using a C/C++ simulator and FPGA emulator with shared register communication, Proc. of DAC, 2004.
27. Mentor Graphics, Platform express and primecell, 2005, http://www.mentor.com/
28. Synopsys, Realview Max-sim ESL Exploration Framework, 2004, http://www.synopsys.com/
29. T.-Y. Chiang, et al, Thermal analysis of heterogeneous 3-D ICs with various integration scenarios, Proc. of IEDM, 2001.
30. A. Rahman, et al., Thermal analysis of three-dimensional integrated circuits, Proc. of IITC, 2001.
31. P. Leduca et al., Challenges for 3d IC integration: bonding quality and thermal management, Proc. of IITC, 2007.
32. K. Puttaswamy, et al., Thermal analysis of a 3d die-stacked high-performance microprocessor, Proc. of GLSVLSI, 2006.
33. A. Jain, et al., Thermal modeling and design of 3D integrated circuits, Proc. of ICTTPES, 2008.