Plasma-induced defect-site generation in si substrate and its impact on performance degradation in scaled MOSFETs

IEEE Electron Device Letters

Volumn 30, Issue 12, 2009, Pages 1275-1277

  Eriguchi, Koji ^a   Nakakubo, Yoshinori ^a   Matsuda, Asahiko ^a   Takao, Yoshinori ^a   Ono, Kouichi ^a  

^a KYOTO UNIVERSITY   (Japan)

Author keywords

Capacitance; Defect site; Device simulation; Drain current; Plasma induced damage (PID)

Indexed keywords

DEFECT SITES; DEVICE SIMULATION; DEVICE SIMULATIONS; PLASMA-INDUCED DAMAGE; PLASMA-INDUCED DAMAGE (PID);

CAPACITANCE; DEFECTS; DEGRADATION; DRAIN CURRENT; ION BOMBARDMENT; PLASMA DIAGNOSTICS; PLASMAS; PROPORTIONAL CONTROL SYSTEMS; SIMULATORS;

DEFECT DENSITY;

EID: 70549110008     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2009.2033726     Document Type: Article

References (17)

1. K. Eriguchi and K. Ono, "Quantitative and comparative characterizations of plasma process-induced damage in advanced metal- oxide-semiconductor devices," J. Phys. D, Appl. Phys., vol.41, no.2, p. 024 002, Jan. 2008.
2. T. Ohchi, S. Kobayashi, M. Fukasawa, K. Kugimiya, T. Kinoshita, T. Takizawa, S. Hamaguchi, Y. Kamide, and T. Tatsumi, "Reducing damage to Si substrates during gate etching processes," Jpn. J. Appl. Phys., vol.47, no.7, pp. 5324-5326, Jul. 2008.
3. K. Eriguchi, A. Matsuda, Y. Nakakubo, M. Kamei, H. Ohta, and K. Ono, "Effects of plasma-induced Si recess structure on n-MOSFET performance degradation," IEEE Electron Device Lett., vol.30, no.7, pp. 712- 714, Jul. 2009.
4. K. Eriguchi, Y. Nakakubo, A. Matsuda, M. Kamei, H. Ohta, H. Nakagawa, S. Hayashi, S. Noda, K. Ishikawa, M. Yoshimaru, and K. Ono, "A new framework for performance prediction of advanced MOSFETs with plasma-induced recess structure and latent defect site," in IEDM Tech. Dig., 2008, pp. 443-446.
5. J. D. Plummer, M. Deal, and P. B. Griffin, Silicon VLSI Technology, Fundamentals, Practice and Modeling. Englewood Cliffs, NJ: Prentice-Hall, 2000.
6. H. Kokura, K. Okabe, M. Nakaishi, and M. Miyajima, "Plasma induced damage on ultra shallow junction in spacer etching," in Proc. Symp. Dry Process, 2005, pp. 27-28.
7. I. W. Wu, R. A. Street, and J. J. C. Mikkelsen, "Damage to shallow n+/p and p+/n junctions by CHF3 + CO2 reactive ion etching," J. Appl. Phys., vol.63, no.5, pp. 1628-1635, Mar. 1988.
8. X. C. Mu, S. J. Fonash, A. Rohatgi, and J. Rieger, "Comparison of the damage and contamination produced by CF4 and CF4/H2 reactive ion etching: The role of hydrogen," Appl. Phys. Lett., vol.48, no.17, pp. 1147-1149, Apr. 1986.
9. A. Henry, O. O. Awadelkarim, J. L. Lindstrom, and G. S. Oehrlein, "Electrical studies on plasma and reactive-ion-etched silicon," J. Appl. Phys., vol.66, no.11, pp. 5388-5393, Dec. 1989.
10. S. A. Vitale and B. A. Smith, "Reduction of silicon recess caused by plasma oxidation during high-density plasma polysilicon gate etching," J. Vac. Sci. Technol. B, Microelectron. Process. Phenom., vol.21, no.5, pp. 2205-2211, Sep. 2003.
11. A. Matsuda, Y. Nakakubo, Y. Ueda, H. Ohta, K. Eriguchi, and K. Ono, "Significance of interface layer between surface layer and Si substrate in plasma-exposed structures and its impacts on plasma-induced damage analysis," in Proc. Ext. Abstr. Solid State Devices Mater., 2008, pp. 358-359.
12. M. A. Lieberman and A. J. Lichtenberg, Principles of Plasma Discharges and Materials Processing, 2nd ed. New York: Wiley-Interscience, 2005.
13. A. M. Goodman, "Metal-Semiconductor barrier height measurement by the differential capacitance method-One carrier system," J. Appl. Phys., vol.34, no.2, pp. 329-338, Feb. 1963.
14. S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley-Interscience, 1981.
15. C. C. McAndrew and P. A. Layman, "MOSFET effective channel length, threshold voltage, and series resistance determination by robust optimization," IEEE Trans. Electron Devices, vol.39, no.10, pp. 2298-2311, Oct. 1992.
16. 2 plasmas," Jpn. J. Appl. Phys., vol. 45, no. 10B, pp. 8157-8162, 2006.
17. G. Hobler and S. Selberherr, "Two-dimensional modeling of ion implantation induced point defects," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.7, no.2, pp. 174-180, Feb. 1988.