Active mode leakage reduction using fine-grained forward body biasing strategy

Integration, the VLSI Journal

Volumn 40, Issue 4, 2007, Pages 561-570

  Khandelwal, Vishal ^a   Srivastava, Ankur ^a  

^a UNIVERSITY OF MARYLAND   (United States)

Author keywords

Algorithm; Design; Forward body biasing; Leakage power optimization

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; ENERGY CONSERVATION; HEURISTIC METHODS; LOGIC DESIGN; PROBLEM SOLVING; THRESHOLD VOLTAGE;

FORWARD BODY BIASING (FBB); GATE LEVEL CIRCUITS; LEAKAGE POWER OPTIMIZATION; STANDARD CELL PLACEMENT;

LEAKAGE CURRENTS;

EID: 34249068015     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.vlsi.2006.12.003     Document Type: Article

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