3-D thin chip integration technology-from technology development to application

2009 IEEE International Conference on 3D System Integration, 3DIC 2009

Volumn , Issue , 2009, Pages

  Fritzsch, T ^a   Mrossko R ^a   Baumgartner, T ^a   Toepper, M ^a   Klein, M ^a   Wolf, J ^a   Wunderle, B ^a,b   Reichl, H ^c  

^a FRAUNHOFER IZM   (Germany)

^b CHEMNITZ UNIVERSITY OF TECHNOLOGY   (Germany)

^c TECHNISCHE UNIVERSITÄT BERLIN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVITY MONITORING; CHIP INTEGRATION; CMOS CHIPS; CORE COMPONENTS; E-CUBES; ELECTRICAL CHARACTERIZATION; EXPERIMENTAL EVALUATION; FLIP CHIP; GERMAN GOVERNMENT; HIGH YIELD; INTEGRATION TECHNOLOGIES; LARGER SUBSTRATES; LIFE-TIMES; MATERIAL FAILURES; METALLIZATIONS; MICROELECTRONIC SYSTEMS; MULTI-LAYER THIN FILM; ON-WAFER; PROCESS STEPS; PROCESSING COSTS; RELIABILITY INVESTIGATIONS; STRESS ACCUMULATION; TECHNOLOGY DEVELOPMENT; TEMPERATURE CYCLE TEST; TEST CHIPS; THERMOMECHANICAL MODEL; THIN CHIPS; THROUGH SILICON VIAS; ULTRA-THIN CHIPS; WAFER-LEVEL PACKAGING TECHNOLOGY;

AUTOMOTIVE INDUSTRY; COMPUTER CRIME; ETCHING; INTEGRATION; MICROELECTRONICS; SILICON WAFERS; SIMULATORS; STRESSES; SUBSTRATES; TECHNOLOGICAL FORECASTING; TECHNOLOGY; THREE DIMENSIONAL;

CHIP SCALE PACKAGES;

EID: 70549098727     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/3DIC.2009.5306578     Document Type: Conference Paper

References (8)

1. M. Töpper et al., "Wafer-Level Chip Size Package (WLCSP)", IEEE Transactions on Advanced Packaging, Vol.23, No.2, May 2000, pp 233-238.
2. B. Wunderle and B. Michel. Lifetime Modeling for Microsystems Integration - from Nano to Systems. J. of Microsystem Technologies, Vol 15, No 6, pp 799.813, Juni 2009
3. P. Ramm, J.M. Wolf and B. Wunderle. Wafer-Level 3-D System Integration.In '3-D IC Integration: Technology and Applications', P.E. Garrou, P. Ramm and C.A. Bower, Editors, Wiley-VCH, 2008
4. M. Töpper et al., "Low Cost Wafer level 3-D Integration without TSV", Electronic Components and Technology Conference-ECTC 2009, May 26-29, 2009, San Diego, California, USA.
5. P.v. Engen et al., "3D Si level integration in wireless sensor node", Proceedings of the Smart System Integration 2009, March 10-11, 2009, Brussels, Belgium.
6. R. van Doremalen et al., "Wireless Activity Monitor Using 3D Integration", DTIP of MEMS&MOEMS 2009, April 1-3, 2009, Rome, Italy.
7. T. Baumgartner et al., "A 3-D Packaging Concept for Cost Effective Packaging of MEMS and ASIC on Wafer Level", EMPC 2009 - European Microelectronics And packaging Conference, June 15-18, 2009, Rimini, Italy.
8. B. Wunderle, R. Mrossko, E. Kaulfersch, O. Wittler, P. Ramm, B. Michel and H. Reichl. Thermo-Mechanical Reliability of 3D-Integrated Structures in Stacked Silicon. (Invited Paper). Mater. Res. Soc. Symp. Proc. Vol. 970, Y02-04, 2007