Low cost wafer-level 3-D integration without TSV

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2009, Pages 339-344

  Töpper, Michael ^a   Baumgartner, Tobias ^a   Klein, Matthias ^a   Fritzsch, Thomas ^a   Roeder, Julia ^a   Lutz, Mario ^a   Von Suchodoletz, Maria ^a   Oppermann, Hermann ^a   Reichl, Herbert ^a  

^a FRAUNHOFER IZM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; 3-D PACKAGES; CARRIER CHIP; CYCLOTENE; DOW CHEMICAL COMPANIES; ELECTRICAL ISOLATION; HIGH COSTS; INTEGRATION TECHNOLOGIES; LOW COST TECHNOLOGY; LOW COSTS; LOW K DIELECTRICS; METALLIZATIONS; NEW APPLICATIONS; ON-WAFER; PACKAGING INDUSTRY; REDISTRIBUTION PROCESS; RELIABILITY TEST; THIN CHIPS; THIN FILM MULTILAYERS; THIN-FILM TECHNOLOGY; THROUGH SILICON VIAS; ULTRA-THIN; ULTRA-THIN CHIPS; WAFER LEVEL;

CHIP SCALE PACKAGES; COSTS; DIELECTRIC MATERIALS; ELECTRONIC EQUIPMENT MANUFACTURE; FILM PREPARATION; INTERCONNECTION NETWORKS; INVESTMENTS; METALLIZING; STANDARDS; TECHNOLOGY; THIN FILM DEVICES; THIN FILMS; THREE DIMENSIONAL; WAFER BONDING;

SILICON WAFERS;

EID: 70349680453     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2009.5074037     Document Type: Conference Paper

References (8)

1. M. Töpper "Wafer Level Chip Size Packaging" in Materials for Advanced Packaging (Hrsg.: D. Lu, C.P. Wong), Springer Verlag 2009, pp 547 - 600, ISBN: 978-0-387- 78218-8
2. E. Beyne "Solving Technical and Economical Barriers to the Adoption of Through-Si-Via 3D Integration Technologies" EPTC 2008
3. 3D IC & TSV Report Cost, Technologies & Markets November 2007 - Last Update
4. M. Töpper, K. Scherpinski, H.-P. Spörle, C. Landesberger, O. Ehrmann, H. Reichl, Thin Chip Integration (TCIModules) - A Novel Technique for Manufacturing Three Dimensional IC-Packages, Proceedings IMAPS 2000, Boston, USA, September 2000.
5. K. Zoschke, J. Wolf, O. Ehrmann, M. Töpper, H. Reichl, "Copper / Benzocyclobutene Multi Layer Wiring - A flexible base Technology for Wafer Level Integration of passive Components" Proceedings 9th Electronics Packaging Technology Conference (EPTC), 10-12 Dec. 2007.
6. M. Töpper, K. Buschick, J. Wolf, V. Glaw, R. Hahn, A. Dabek, O. Ehrmann, H. Reichl, Embedding Technology - A Chip First Approach using BCB, Advancing Microelectronics Vol24, No.4, July/August 1997.
7. M. Töpper, A. Achen, H. Reichl, Interfacial Adhesion Analysis of BCB / TiW / Cu / PbSn Technology in Waferlevel Packaging, Proceedings ECTC 2003, Las Vegas, June 2003.
8. M. Töpper, S. Fehlberg, K. Scherpinski, C. Karduck, V. Glaw, K. Heinricht, P. Coskina, O. Ehrmann, H. Reichl, Wafer-Level Chip Size Package (WL-CSP), IEEE-CPMT, Advanced Packaging June 2000.