Validation of the porous-medium approach to model interlayer-cooled 3D-chip stacks

2009 IEEE International Conference on 3D System Integration, 3DIC 2009

Volumn , Issue , 2009, Pages

  Brunschwiler, T ^a   Paredes, S ^a   Drechsler, U ^a   Michel, B ^a   Cesar, W ^b   Toral G ^b   Temiz, Y ^b   Leblebici, Y ^b  

^a IBM RESEARCH ZURICH   (Switzerland)

^b EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

CONVECTIVE HEAT DISSIPATION; EXPERIMENTAL VALIDATIONS; FLOOR-PLANNING; FLUID DELIVERY; FLUID VELOCITIES; HEAT FLOWS; HEAT REMOVAL; HEAT TRANSFER STRUCTURES; HOT SPOT; JUNCTION TEMPERATURES; LOW POROSITY; MULTI-SCALE MODELING; MULTIPLE CAVITIES; NONUNIFORMITY; PIN-FINS; POROUS-MEDIA; SOLID-SOLID INTERFACES; SUBDOMAIN; SYSTEM LEVELS; TEMPERATURE RESPONSE; THERMAL FIELD; TOTAL POWER;

FINS (HEAT EXCHANGE); FLUIDS; HEAT EXCHANGERS; HEAT FLUX; HEAT TRANSFER; MICROCHANNELS; PARAMETER EXTRACTION; THREE DIMENSIONAL;

PHASE INTERFACES;

EID: 70549083736     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/3DIC.2009.5306530     Document Type: Conference Paper

References (9)

1. International Technology Roadmap for Semiconductors (ITRS), 2008 Update - Packaging and Assembly http://www.itrs.net/Links/2008ITRS/Update/2008-Update. pdf
2. T. Brunschwiler, H. Rothuizen, U. Kloter, H. Reichl, B. Wunderle, H. Oppermann, B. Michel, "Forced Convective Interlayer Cooling Potential in Vertically Integrated Packages", Proc. 11th "ITHERM 2008," Orlando, FL, May 2008 (IEEE, 2008), pp. 1114-1125.
3. Y. Peles, A. Kosar, C. Mishra, C. Kuo, and B. Schneider, "Forced Convective Heat Transfer across a Pin Fin Micro Heat Sink", Int. J. Heat Mass Transfer, 2005, Vol. 48, 3615-3627.
4. T. Brunschwiler, B. Michel, H. Rothuizen, U. Kloter, B. Wunderle, H. Oppermann, and H. Reichl, "Interlayer Cooling Potential in Vertically Integrated Packages", Microsystem Technol., Vol. 15, No. 1, pp. 57-74 (2009, published online August 21, 2008).
5. E.G. Colgan et al., "A Practical Implementation of Silicon Microchannel Coolers for High Power Chips", IEEE Trans. Components Packaging Technol., Vol. 30, No. 2., June 2007, 218-225.
6. T. Brunschwiler, H. Rothuizen, U. Kloter, H. Reichl, B. Wunderle, H. Oppermann, B. Michel, " Hotspot-optimized interlayer cooling in vertically integrated packages ", Proc. MRS fall meeting 2008 p.223-234, Boston, MA, December 2008.
7. K. Takahashi et al., "Process Integration of 3D Chip Stack with Vertical Interconnection", Proc. 54th IEEE Electronic Components and Technology Conference, 2004, Vol. 1, 601-609.
8. X. Chen, K. Toh, and J. Chai, "Direct Liquid Cooling of a Stacked Multichip Module", Proc. Electronics Packaging Technology Conference, 2002, 380-384.
9. R. Waelchli, T. Bruschwiler, B. Michel, and D. Poulikakos, "Combined local microchannel-scale CFD modeling and global chip scale network modeling for electronics cooling design", International Journal of Heat and Mass Transfer, in-press (2009).