Exploiting fine-grained data parallelism with chip multiprocessors and fast barriers

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2006, Pages 235-246

  Sampson, Jack ^a   González, Rubén ^b,c   Collard, Jean Francois ^c   Jouppi, Norman P ^c   Schlansker, Mike ^c   Calder, Brad ^d  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^c HEWLETT PACKARD LABORATORIES   (United States)

^d MICROSOFT   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP MULTIPROCESSORS; FINE GRAINED DATA PARALLELISM;

COMMUNICATION SYSTEMS; COMPUTER HARDWARE; PROGRAM PROCESSORS; SUPPORT VECTOR MACHINES;

DATA ACQUISITION;

EID: 40349086066     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2006.23     Document Type: Conference Paper

References (26)