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Volumn , Issue , 2009, Pages

Exploiting DMA to enable non-blocking execution in decoupled threaded architecture

Author keywords

[No Author keywords available]

Indexed keywords

BRANCH PREDICTORS; DATA PATTERNS; DISTRIBUTED HARDWARE; EXECUTION TIME; FRAME MEMORY; GLOBAL DATA; LOCAL VARIABLES; NON-BLOCKING; PREFETCHES; PREFETCHING; SYNCHRONIZATION DATA; THREAD-LEVEL PARALLELISM;

EID: 70449913551     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2009.5161111     Document Type: Conference Paper
Times cited : (11)

References (16)
  • 1
    • 70449841528 scopus 로고    scopus 로고
    • G. Almási, C. Casçaval, J. G. Castańos, M. Denneau, D. Lieber, J. E. Moreira, and H. S. Warren, Jr., Dissecting cyclops: a detailed analysis of a multithreaded architecture, SIGARCH Comput. Archit. News, 31, no. 1, pp. 26-38, 2003.
    • G. Almási, C. Casçaval, J. G. Castańos, M. Denneau, D. Lieber, J. E. Moreira, and H. S. Warren, Jr., "Dissecting cyclops: a detailed analysis of a multithreaded architecture," SIGARCH Comput. Archit. News, vol. 31, no. 1, pp. 26-38, 2003.
  • 2
    • 51349168284 scopus 로고    scopus 로고
    • M. Shah, J. Barreh, J. Brooks, R. Golla, G. Grohoski, N. Gura, R. Hetherington, P. Jordan, M. Luttrell, C. Olson et al., UltraSPARC T2: A highly-treaded, power-efficient, SPARC SOC, in Solid-State Circuits Conference, 2007. ASSCC'07. IEEE Asian, Jeju, Republic of Korea, 2007, pp. 22-25.
    • M. Shah, J. Barreh, J. Brooks, R. Golla, G. Grohoski, N. Gura, R. Hetherington, P. Jordan, M. Luttrell, C. Olson et al., "UltraSPARC T2: A highly-treaded, power-efficient, SPARC SOC," in Solid-State Circuits Conference, 2007. ASSCC'07. IEEE Asian, Jeju, Republic of Korea, 2007, pp. 22-25.
  • 4
    • 70350380019 scopus 로고    scopus 로고
    • Online, Available
    • "Plurality architecture." [Online]. Available: http://www.plurality.com/architecture.html
    • Plurality architecture
  • 6
    • 47249097035 scopus 로고    scopus 로고
    • DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems
    • Gramado, Brasil, Oct
    • R. Giorgi, Z. Popovic, and N. Puzovic, "DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems," in Proceedings of IEEE SBAC-PAD, Gramado, Brasil, Oct. 2007, pp. 263-270.
    • (2007) Proceedings of IEEE SBAC-PAD , pp. 263-270
    • Giorgi, R.1    Popovic, Z.2    Puzovic, N.3
  • 7
    • 57649199756 scopus 로고    scopus 로고
    • Analyzing scalability of deblocking filter of h.264 via tlp exploitation in a new many-core architecture
    • Parma, Italy, sept
    • R. Giorgi, Z. Popovic, N. Puzovic, A. Azavedo, and B. Juurlink, "Analyzing scalability of deblocking filter of h.264 via tlp exploitation in a new many-core architecture," in Proceedings of the 11th EUROMICRO-DSD, Parma, Italy, sept 2008, pp. 189-194.
    • (2008) Proceedings of the 11th EUROMICRO-DSD , pp. 189-194
    • Giorgi, R.1    Popovic, Z.2    Puzovic, N.3    Azavedo, A.4    Juurlink, B.5
  • 8
    • 70450085838 scopus 로고    scopus 로고
    • R. Giorgi, Z. Popovic, and N. Puzovic, Introducing hardware tlp support for the cell processor, in Proceedings of IEEE International Workshop on Multi-Core Computing Systems. Fukuoka, Japan: IEEE, March 16-19, 2009 2009, pp. 1-6, accepted for publication.
    • R. Giorgi, Z. Popovic, and N. Puzovic, "Introducing hardware tlp support for the cell processor," in Proceedings of IEEE International Workshop on Multi-Core Computing Systems. Fukuoka, Japan: IEEE, March 16-19, 2009 2009, pp. 1-6, accepted for publication.
  • 9
    • 0035416089 scopus 로고    scopus 로고
    • Scheduled dataflow: Execution paradigm, architecture, and performance evaluation
    • Aug
    • K. M. Kavi, R. Giorgi, and J. Arul, "Scheduled dataflow: Execution paradigm, architecture, and performance evaluation," IEEE Transaction on Computers, vol. 50, no. 8, pp. 834-846, Aug. 2001.
    • (2001) IEEE Transaction on Computers , vol.50 , Issue.8 , pp. 834-846
    • Kavi, K.M.1    Giorgi, R.2    Arul, J.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.