-
1
-
-
70449841528
-
-
G. Almási, C. Casçaval, J. G. Castańos, M. Denneau, D. Lieber, J. E. Moreira, and H. S. Warren, Jr., Dissecting cyclops: a detailed analysis of a multithreaded architecture, SIGARCH Comput. Archit. News, 31, no. 1, pp. 26-38, 2003.
-
G. Almási, C. Casçaval, J. G. Castańos, M. Denneau, D. Lieber, J. E. Moreira, and H. S. Warren, Jr., "Dissecting cyclops: a detailed analysis of a multithreaded architecture," SIGARCH Comput. Archit. News, vol. 31, no. 1, pp. 26-38, 2003.
-
-
-
-
2
-
-
51349168284
-
-
M. Shah, J. Barreh, J. Brooks, R. Golla, G. Grohoski, N. Gura, R. Hetherington, P. Jordan, M. Luttrell, C. Olson et al., UltraSPARC T2: A highly-treaded, power-efficient, SPARC SOC, in Solid-State Circuits Conference, 2007. ASSCC'07. IEEE Asian, Jeju, Republic of Korea, 2007, pp. 22-25.
-
M. Shah, J. Barreh, J. Brooks, R. Golla, G. Grohoski, N. Gura, R. Hetherington, P. Jordan, M. Luttrell, C. Olson et al., "UltraSPARC T2: A highly-treaded, power-efficient, SPARC SOC," in Solid-State Circuits Conference, 2007. ASSCC'07. IEEE Asian, Jeju, Republic of Korea, 2007, pp. 22-25.
-
-
-
-
3
-
-
0037669851
-
Exploiting ilp, tlp, and dlp with the polymorphous trips architecture
-
K. Sankaralingam, R. Nagarajan, H. Liu, C. Kim, J. Huh, D. Burger, S. W. Keckler, and C. R. Moore, "Exploiting ilp, tlp, and dlp with the polymorphous trips architecture," SIGARCH Comput. Archit. News, vol. 31, no. 2, pp. 422-433, 2003.
-
(2003)
SIGARCH Comput. Archit. News
, vol.31
, Issue.2
, pp. 422-433
-
-
Sankaralingam, K.1
Nagarajan, R.2
Liu, H.3
Kim, C.4
Huh, J.5
Burger, D.6
Keckler, S.W.7
Moore, C.R.8
-
4
-
-
70350380019
-
-
Online, Available
-
"Plurality architecture." [Online]. Available: http://www.plurality.com/architecture.html
-
Plurality architecture
-
-
-
5
-
-
34548858682
-
An 80-Tile 1.28 TFLOPS Network-on-Chip in 65nm CMOS
-
S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, P. Iyer, A. Singh, T. Jacob et al., "An 80-Tile 1.28 TFLOPS Network-on-Chip in 65nm CMOS," in Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International, 2007, pp. 98-589.
-
(2007)
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
, pp. 98-589
-
-
Vangal, S.1
Howard, J.2
Ruhl, G.3
Dighe, S.4
Wilson, H.5
Tschanz, J.6
Finan, D.7
Iyer, P.8
Singh, A.9
Jacob, T.10
-
6
-
-
47249097035
-
DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems
-
Gramado, Brasil, Oct
-
R. Giorgi, Z. Popovic, and N. Puzovic, "DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems," in Proceedings of IEEE SBAC-PAD, Gramado, Brasil, Oct. 2007, pp. 263-270.
-
(2007)
Proceedings of IEEE SBAC-PAD
, pp. 263-270
-
-
Giorgi, R.1
Popovic, Z.2
Puzovic, N.3
-
7
-
-
57649199756
-
Analyzing scalability of deblocking filter of h.264 via tlp exploitation in a new many-core architecture
-
Parma, Italy, sept
-
R. Giorgi, Z. Popovic, N. Puzovic, A. Azavedo, and B. Juurlink, "Analyzing scalability of deblocking filter of h.264 via tlp exploitation in a new many-core architecture," in Proceedings of the 11th EUROMICRO-DSD, Parma, Italy, sept 2008, pp. 189-194.
-
(2008)
Proceedings of the 11th EUROMICRO-DSD
, pp. 189-194
-
-
Giorgi, R.1
Popovic, Z.2
Puzovic, N.3
Azavedo, A.4
Juurlink, B.5
-
8
-
-
70450085838
-
-
R. Giorgi, Z. Popovic, and N. Puzovic, Introducing hardware tlp support for the cell processor, in Proceedings of IEEE International Workshop on Multi-Core Computing Systems. Fukuoka, Japan: IEEE, March 16-19, 2009 2009, pp. 1-6, accepted for publication.
-
R. Giorgi, Z. Popovic, and N. Puzovic, "Introducing hardware tlp support for the cell processor," in Proceedings of IEEE International Workshop on Multi-Core Computing Systems. Fukuoka, Japan: IEEE, March 16-19, 2009 2009, pp. 1-6, accepted for publication.
-
-
-
-
9
-
-
0035416089
-
Scheduled dataflow: Execution paradigm, architecture, and performance evaluation
-
Aug
-
K. M. Kavi, R. Giorgi, and J. Arul, "Scheduled dataflow: Execution paradigm, architecture, and performance evaluation," IEEE Transaction on Computers, vol. 50, no. 8, pp. 834-846, Aug. 2001.
-
(2001)
IEEE Transaction on Computers
, vol.50
, Issue.8
, pp. 834-846
-
-
Kavi, K.M.1
Giorgi, R.2
Arul, J.3
-
10
-
-
0001197768
-
TAM-A Compiler Controlled Threaded Abstract Machine
-
D. Culler, S. Goldstein, K. Schauser, and T. Von Eicken, "TAM-A Compiler Controlled Threaded Abstract Machine," Journal of Parallel and Distributed Computing, vol. 18, no. 3, pp. 347-370, 1993.
-
(1993)
Journal of Parallel and Distributed Computing
, vol.18
, Issue.3
, pp. 347-370
-
-
Culler, D.1
Goldstein, S.2
Schauser, K.3
Von Eicken, T.4
-
11
-
-
0029179467
-
A design study of the EARTH multiprocessor
-
IFIP Working Group on Algol Manchester, UK, UK
-
H. Hum, O. Maquelin, K. Theobald, X. Tian, X. Tang, G. Gao, P. Cupryk, N. Elmasri, L. Hendren, A. Jimenez et al., "A design study of the EARTH multiprocessor," in Proceedings of the IFIP WG10. 3 working conference on Parallel architectures and compilation techniques table of contents. IFIP Working Group on Algol Manchester, UK, UK, 1995, pp. 59-68.
-
(1995)
Proceedings of the IFIP WG10. 3 working conference on Parallel architectures and compilation techniques table of contents
, pp. 59-68
-
-
Hum, H.1
Maquelin, O.2
Theobald, K.3
Tian, X.4
Tang, X.5
Gao, G.6
Cupryk, P.7
Elmasri, N.8
Hendren, L.9
Jimenez, A.10
-
12
-
-
33646922057
-
The future of wires
-
R. Ho, K. W. Mai, and M. A. Horowitz, "The future of wires," in Proceedings of the IEEE, 2001, pp. 490-504.
-
(2001)
Proceedings of the IEEE
, pp. 490-504
-
-
Ho, R.1
Mai, K.W.2
Horowitz, M.A.3
-
13
-
-
70349744879
-
A module-based cell processor simulator
-
L'Aquila, Italy, Jul
-
F. Cabarcas, A. Rico, D. Rodenas, X. Martorell, A. Ramirez, and E. Ayguade, "A module-based cell processor simulator," in HiPEAC ACACES-2007, L'Aquila, Italy, Jul. 2007, pp. 279-282.
-
(2007)
HiPEAC ACACES-2007
, pp. 279-282
-
-
Cabarcas, F.1
Rico, A.2
Rodenas, D.3
Martorell, X.4
Ramirez, A.5
Ayguade, E.6
-
14
-
-
36749086936
-
UNISIM: An Open Simulation Environment and Library for Complex Architecture Design and Collaborative Development
-
D. August, J. Chang, S. Girbal, D. Gracia-Perez, G. Mouchard, D. Penry, O. Temam, and N. Vachharajani, "UNISIM: An Open Simulation Environment and Library for Complex Architecture Design and Collaborative Development," Computer Architecture Letters, vol. 6, no. 2, pp. 45-48, 2007.
-
(2007)
Computer Architecture Letters
, vol.6
, Issue.2
, pp. 45-48
-
-
August, D.1
Chang, J.2
Girbal, S.3
Gracia-Perez, D.4
Mouchard, G.5
Penry, D.6
Temam, O.7
Vachharajani, N.8
-
15
-
-
84962779213
-
MiBench: A free, commercially representative embedded benchmark suite
-
M. Guthaus, J. Ringenberg, D. Ernst, T. Austin, T. Mudge, and R. Brown, "MiBench: A free, commercially representative embedded benchmark suite," in Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop on, 2001, pp. 3-14.
-
(2001)
Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop on
, pp. 3-14
-
-
Guthaus, M.1
Ringenberg, J.2
Ernst, D.3
Austin, T.4
Mudge, T.5
Brown, R.6
-
16
-
-
33746635665
-
Data-Driven Multithreading Using Conventional Microprocessors
-
C. Kyriacou, P. Evripidou, and P. Trancoso, "Data-Driven Multithreading Using Conventional Microprocessors," IEEE Transactions On Parallel and Distributed Systems, pp. 1176-1188, 2006.
-
(2006)
IEEE Transactions On Parallel and Distributed Systems
, pp. 1176-1188
-
-
Kyriacou, C.1
Evripidou, P.2
Trancoso, P.3
|