Scheduled dataflow: Execution paradigm, architecture, and performance evaluation

IEEE Transactions on Computers

Volumn 50, Issue 8, 2001, Pages 834-846

  Kavi, Krishna M ^b   Giorgi, Roberto ^a,c   Arul, Joseph ^a,b  

^a IEEE

^b UNIVERSITY OF ALABAMA IN HUNTSVILLE   (United States)

^c UNIVERSITY OF SIENA   (Italy)

Author keywords

Dataflow architectures; Decoupled architectures; Multithreaded architectures; Superscalar; Thread level parallelism

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER PROGRAMMING; DATA STORAGE EQUIPMENT; PARALLEL PROCESSING SYSTEMS; SCHEDULING; VERY LONG INSTRUCTION WORD ARCHITECTURE;

DATA FLOW ARCHITECTURES; DECOUPLED ARCHITECTURES; MULTITHREADED ARCHITECTURES; THREAD LEVEL PARALLELISM;

DATA FLOW ANALYSIS;

EID: 0035416089     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.947003     Document Type: Article

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