-
1
-
-
33747566850
-
3-d ics: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration
-
May
-
K. Banerjee, S. Souri, P. Kapur, and K. Saraswat. 3-d ics: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. Proceedings of the IEEE, 89(5):602-633, May 2001.
-
(2001)
Proceedings of the IEEE
, vol.89
, Issue.5
, pp. 602-633
-
-
Banerjee, K.1
Souri, S.2
Kapur, P.3
Saraswat, K.4
-
2
-
-
64349118463
-
A wafer-scale 3-D circuit integration technology
-
October
-
J. Burns, B. Aull, C. Chen, C.-L. Chen, C. Keast, J. Knecht, V. Suntharalingam, K. Warner, P. Wyatt, and D. Yost. A wafer-scale 3-D circuit integration technology. IEEE Transactions on Electron Devices, 53(10):2507-2516, October 2006.
-
(2006)
IEEE Transactions on Electron Devices
, vol.53
, Issue.10
, pp. 2507-2516
-
-
Burns, J.1
Aull, B.2
Chen, C.3
Chen, C.-L.4
Keast, C.5
Knecht, J.6
Suntharalingam, V.7
Warner, K.8
Wyatt, P.9
Yost, D.10
-
3
-
-
84968470212
-
An algorithm for the machine calculation of complex fourier series
-
J. W. Cooley and J. W. Tukey. An algorithm for the machine calculation of complex fourier series. Mathematics of Computation, 19(90):297-301, 1965.
-
(1965)
Mathematics of Computation
, vol.19
, Issue.90
, pp. 297-301
-
-
Cooley, J.W.1
Tukey, J.W.2
-
4
-
-
84954424983
-
Design tools for 3-d integrated circuits
-
New York, NY, USA, ACM
-
S. Das, A. Chandrakasan, and R. Reif. Design tools for 3-d integrated circuits. In ASPDAC: Proceedings of the 2003 conference on Asia South Pacic design automation, pages 53-56, New York, NY, USA, 2003. ACM.
-
(2003)
ASPDAC: Proceedings of the 2003 conference on Asia South Pacic design automation
, pp. 53-56
-
-
Das, S.1
Chandrakasan, A.2
Reif, R.3
-
5
-
-
28344452134
-
Demystifying 3D ICs: The Pros and Cons of Going Vertical
-
22(6):498{510, Nov.-Dec
-
W. R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A. M. Sule, M. Steer, and P. D. Franzon. Demystifying 3D ICs: The Pros and Cons of Going Vertical. IEEE Design And Test of Computers, 22(6):498{510, Nov.-Dec. 2005.
-
(2005)
IEEE Design And Test of Computers
-
-
Davis, W.R.1
Wilson, J.2
Mick, S.3
Xu, J.4
Hua, H.5
Mineo, C.6
Sule, A.M.7
Steer, M.8
Franzon, P.D.9
-
6
-
-
0034819418
-
Interconnect characteristics of 2.5-d system integration scheme
-
New York, NY, USA, ACM
-
Y. Deng and W. P. Maly. Interconnect characteristics of 2.5-d system integration scheme. In ISPD '01: Proceedings of the 2001 international symposium on Physical design, pages 171-175, New York, NY, USA, 2001. ACM.
-
(2001)
ISPD '01: Proceedings of the 2001 international symposium on Physical design
, pp. 171-175
-
-
Deng, Y.1
Maly, W.P.2
-
7
-
-
33750919241
-
-
R. Hentschke, G. Flach, F. Pinto, and R. Reis. Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing. In SBCCI '06: Proceedings of the 19th annual symposium on Integrated circuits and systems design, pages 220-225, New York, NY, USA, 2006. ACM.
-
R. Hentschke, G. Flach, F. Pinto, and R. Reis. Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing. In SBCCI '06: Proceedings of the 19th annual symposium on Integrated circuits and systems design, pages 220-225, New York, NY, USA, 2006. ACM.
-
-
-
-
8
-
-
33646922057
-
The Future of Wires
-
R. Ho, K. Mai, and M. Horowitz. The Future of Wires. Proceedings of the IEEE, 89(4):490-504, 2001.
-
(2001)
Proceedings of the IEEE
, vol.89
, Issue.4
, pp. 490-504
-
-
Ho, R.1
Mai, K.2
Horowitz, M.3
-
10
-
-
59349109019
-
Parallel merge algorithm for high-throughput signal processing applications
-
N. Moezzi-Madani and W. Davis. Parallel merge algorithm for high-throughput signal processing applications. Electronics Letters, 45(3):188-189, 2009.
-
(2009)
Electronics Letters
, vol.45
, Issue.3
, pp. 188-189
-
-
Moezzi-Madani, N.1
Davis, W.2
-
11
-
-
34548782738
-
FreePDK: An Open-Source Variation-Aware Design Kit
-
IEEE Computer Society Washington, DC, USA
-
J. Stine, I. Castellanos, M. Wood, J. Henson, F. Love, W. Davis, P. Franzon, M. Bucher, S. Basavarajaiah, J. Oh, et al. FreePDK: An Open-Source Variation-Aware Design Kit. In Proceedings of the 2007 IEEE International Conference on Microelectronic Systems Education, pages 173-174. IEEE Computer Society Washington, DC, USA, 2007.
-
(2007)
Proceedings of the 2007 IEEE International Conference on Microelectronic Systems Education
, pp. 173-174
-
-
Stine, J.1
Castellanos, I.2
Wood, M.3
Henson, J.4
Love, F.5
Davis, W.6
Franzon, P.7
Bucher, M.8
Basavarajaiah, S.9
Oh, J.10
-
12
-
-
64949106457
-
-
K. Sun, X. Dong, Y. Xie, J. Li, and Y. Chen. A novel architecture of the 3d stacked mram l2 cache for cmps. High Performance Computer Architecture, 2009. HPCA 2009. IEEE 15th International Symposium on, pages 239{249, Feb. 2009.
-
K. Sun, X. Dong, Y. Xie, J. Li, and Y. Chen. A novel architecture of the 3d stacked mram l2 cache for cmps. High Performance Computer Architecture, 2009. HPCA 2009. IEEE 15th International Symposium on, pages 239{249, Feb. 2009.
-
-
-
-
13
-
-
28144458334
-
Megapixel cmos image sensor fabricated in three-dimensional integrated circuit technology
-
Feb
-
V. Suntharalingam, R. Berger, J. Burns, C. Chen, C. Keast, J. Knecht, R. Lambert, K. Newcomb, D. O'Mara, D. Rathman, D. Shaver, A. Soares, C. Stevenson, B. Tyrrell, K. Warner, B. Wheeler, D.-R. Yost, and D. Young. Megapixel cmos image sensor fabricated in three-dimensional integrated circuit technology. Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International, pages 356-357 Vol. 1, Feb. 2005.
-
(2005)
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
, vol.1
, pp. 356-357
-
-
Suntharalingam, V.1
Berger, R.2
Burns, J.3
Chen, C.4
Keast, C.5
Knecht, J.6
Lambert, R.7
Newcomb, K.8
O'Mara, D.9
Rathman, D.10
Shaver, D.11
Soares, A.12
Stevenson, C.13
Tyrrell, B.14
Warner, K.15
Wheeler, B.16
Yost, D.-R.17
Young, D.18
-
14
-
-
0030149507
-
-
S. Wilton and N. Jouppi. CACTI: an enhanced cache access and cycle time model. Solid-State Circuits, IEEE Journal of, 31(5):677-688, 1996.
-
S. Wilton and N. Jouppi. CACTI: an enhanced cache access and cycle time model. Solid-State Circuits, IEEE Journal of, 31(5):677-688, 1996.
-
-
-
-
16
-
-
34250769511
-
Cascade: A standard supercell design methodology with congestion-driven placement for three-dimensional interconnect-heavy very large-scale integrated circuits
-
July
-
L. Zhou, C. Wakayama, and C.-J. Shi. Cascade: A standard supercell design methodology with congestion-driven placement for three-dimensional interconnect-heavy very large-scale integrated circuits. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 26(7):1270-1282, July 2007.
-
(2007)
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
, vol.26
, Issue.7
, pp. 1270-1282
-
-
Zhou, L.1
Wakayama, C.2
Shi, C.-J.3
|