Dynamic voltage and frequency management for a low-power embedded microprocessor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Akui, Satoshi ^a   Seno, Katsunori ^a   Nakai, Masakatsu ^a   Meguro, Tetsumasa ^a   Seki, Takahiro ^a   Kondo, Tetsuo ^a   Hashiguchi, Akihiko ^a   Kawahara, Hirokazu ^a   Kumano, Kazuo ^a   Shimura, Masayuki ^a  

^a SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CENTRAL PROCESSING UNIT (CPU); CLOCK FREQUENCY; POWER CONSUMPTION;

DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC CLOCKS; ELECTRIC CONVERTERS; ELECTRIC FREQUENCY CONTROL; FLIP FLOP CIRCUITS; FREQUENCIES; LEAKAGE CURRENTS; LSI CIRCUITS; PERSONAL DIGITAL ASSISTANTS;

MICROPROCESSOR CHIPS;

EID: 2442716255     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. P. Macken et al., "A Voltage Reduction Technique for Digital Systems," ISSCC Dig. Tech. Papers, pp. 238-239, Feb. 1990.
2. K. Suzuki et al., "A 300MIPS/W RISC Core Processor with Variable Supply-Voltage Scheme in Variable Threshold-Voltage CMOS," Proc. CICC, pp. 587-590, May 1997.
3. S. Sakiyama et al., "A Lean Power Management Technique: The Lowest Power Consumption for the Given Operating Speed of LSIs," Symposium on VLSI Circuits Dig., pp. 99-100, Jun. 1997.
4. T. Burd, et al., "A Dynamic Voltage Scaled Microprocessor System," ISSCC Dig. Tech. Papers, pp.294-295, Feb. 2000.
5. K. Nowka, et al., "A 0.9V to 1.95V Dynamic Voltage-Scalable and Frequency-Scalable 32b PowerPC Processor," ISSCC Dig. Tech. Papers, pp. 340-341, Feb. 2002.