A hybrid spur compensation technique for finite-modulo fractional-n phase-locked loops

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 11, 2009, Pages 2922-2934

  Zhang, Li ^a   Yu, Xueyi ^a   Sun, Yuanfeng ^a   Rhee, Woogeun ^a   Wang, Dawn ^b   Wang, Zhihua ^a   Chen, Hongyi ^a  

^a TSINGHUA UNIVERSITY   (China)

^b IBM   (United States)

Author keywords

Fractional N; Frequency synthesizer; Integrated circuits; Phase noise; PLL; Spur reduction

Indexed keywords

CHARGE COMPENSATION; CHARGE PUMP; COMPENSATION CIRCUITS; COMPENSATION CURRENTS; COMPENSATION TECHNIQUES; DIGITAL MODULATORS; DYNAMIC RANGE; FOURTH-ORDER; FRACTIONAL-N; FRACTIONAL-N PHASE-LOCKED LOOPS; FREQUENCY RESOLUTIONS; HIGH-ORDER; PHASE INTERPOLATION; PLL; QUANTIZATION NOISE; SPUR REDUCTION; TIME DOMAIN; VOLTAGE DOMAINS;

DIGITAL CIRCUITS; FREQUENCY SYNTHESIZERS; INTEGRATED CIRCUITS; MODULATION; MODULATORS; PHASE NOISE;

PHASE LOCKED LOOPS;

EID: 70449495520     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2028927     Document Type: Article

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