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Volumn , Issue , 2008, Pages 417-420

A hybrid spur compensation technique for finite-modulo fractional-N phase-locked loops

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE COMPENSATION; CHARGE PUMP; COMPENSATION CIRCUITS; COMPENSATION CURRENTS; COMPENSATION TECHNIQUES; DIGITAL MODULATORS; DYNAMIC RANGE; FRACTIONAL-N; FRACTIONAL-N PHASE-LOCKED LOOPS; HIGH-ORDER; PHASE INTERPOLATION; QUANTIZATION NOISE; TIME DOMAIN; VOLTAGE DOMAINS;

EID: 67649973959     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2008.4708816     Document Type: Conference Paper
Times cited : (4)

References (8)
  • 1
    • 49549098193 scopus 로고    scopus 로고
    • A lGHz fractional-N PLL clock generator with low-OSR δ∑ modulation and FIR-embedded noise filtering
    • Feb
    • X. Yu, Y. Sun, L. Zhang, W. Rhee, and Z. Wang, "A lGHz fractional-N PLL clock generator with low-OSR δ∑ modulation and FIR-embedded noise filtering," ISSCC Dig. Tech. Papers, pp. 346-347, Feb. 2008.
    • (2008) ISSCC Dig. Tech. Papers , pp. 346-347
    • Yu, X.1    Sun, Y.2    Zhang, L.3    Rhee, W.4    Wang, Z.5
  • 2
    • 0035335391 scopus 로고    scopus 로고
    • A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching
    • May
    • C. H. Park, O. Kim, and B. Kim, "A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching," IEEE J. of Solid-State Circuits, vol. 36, pp. 777-783, May 2001.
    • (2001) IEEE J. of Solid-State Circuits , vol.36 , pp. 777-783
    • Park, C.H.1    Kim, O.2    Kim, B.3
  • 3
    • 0008975984 scopus 로고    scopus 로고
    • An on-chip phase compensation technique in fractional-N frequency synthesis
    • May
    • W. Rhee and A. Ali, "An on-chip phase compensation technique in fractional-N frequency synthesis," in Proc. ISCAS, May 1999, pp. 363- 366.
    • (1999) Proc. ISCAS , pp. 363-366
    • Rhee, W.1    Ali, A.2
  • 4
    • 38849121237 scopus 로고    scopus 로고
    • Fast-locking hybrid PLL combining integer & fractional divisions
    • June
    • K. Woo, Y. Liu, and D. Ham, "Fast-locking hybrid PLL combining integer & fractional divisions," 2007 Symp. on VLSI Circuits, June 2007, pp. 260-261.
    • (2007) 2007 Symp. on VLSI Circuits , pp. 260-261
    • Woo, K.1    Liu, Y.2    Ham, D.3
  • 5
    • 0013343334 scopus 로고    scopus 로고
    • New fast-lock PLL for mobile GSM GPRS applications
    • Sept
    • B. Memmler, E. Gotz, and G. Schonleber, "New fast-lock PLL for mobile GSM GPRS applications," in Proc. ESSCIRC'OO, Sept. 2000, pp. 468-471.
    • (2000) Proc. ESSCIRC'OO , pp. 468-471
    • Memmler, B.1    Gotz, E.2    Schonleber, G.3
  • 6
    • 84893748678 scopus 로고    scopus 로고
    • A 2GHz δ∑ fractional-N frequency PLL in 0.35μm CMOS
    • Sept
    • R. Ahola and K. Halonen, "A 2GHz δ∑ fractional-N frequency PLL in 0.35μm CMOS," in Proc. ESSCIRC'OO, Sept. 2000, pp. 472-475.
    • (2000) Proc. ESSCIRC'OO , pp. 472-475
    • Ahola, R.1    Halonen, K.2
  • 7
    • 34548830412 scopus 로고    scopus 로고
    • A wide-bandwidth 2.4GHz ISM-band fractional-N PLL with adaptive phase-noise cancellation
    • Feb
    • A. Swaminathan, K. Wang, and I. Galton, "A wide-bandwidth 2.4GHz ISM-band fractional-N PLL with adaptive phase-noise cancellation," ISSCC Dig. Tech. Papers, pp. 302-303, Feb. 2007.
    • (2007) ISSCC Dig. Tech. Papers , pp. 302-303
    • Swaminathan, A.1    Wang, K.2    Galton, I.3
  • 8
    • 33749182792 scopus 로고    scopus 로고
    • An on-chip jitter measurement circuit with sub-picosecond resolution
    • Sept
    • K. Jenkins, A. P. Jose, and D. F. Heidel, "An on-chip jitter measurement circuit with sub-picosecond resolution," in Proc. ESSCIRC'05, Sept. 2005, pp. 157-160.
    • (2005) Proc. ESSCIRC'05 , pp. 157-160
    • Jenkins, K.1    Jose, A.P.2    Heidel, D.F.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.