A 1.255 GHz clock generator with high-bandwidth supply-rejection using a regulated-replica regulator in 45-nm CMOS

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 11, 2009, Pages 2901-2910

  Toifl, Thomas ^a   Menolfi, Christian ^a   Buchmann, Peter ^a   Kossel, Marcel ^a   Morf, Thomas ^a   Schmatz, Martin L ^a  

^a IBM RESEARCH ZURICH   (Switzerland)

Author keywords

CDR; Clock generation; CMOS style clocking; DLL; Low dropout regulator; Phase rotator; Regulated replica; Replica regulator; Supply regulation; Voltage regulator

Indexed keywords

CDR; CLOCK GENERATION; CMOS-STYLE CLOCKING; DLL; LOW-DROPOUT REGULATOR; PHASE-ROTATOR; REGULATED REPLICA; REPLICA REGULATOR; SUPPLY REGULATION;

ANALOG TO DIGITAL CONVERSION; ELECTRIC CLOCKS; ELECTRIC POTENTIAL; INTEGRATED CIRCUIT TESTING; ROTATION; SILICON ON INSULATOR TECHNOLOGY; VOLTAGE CONTROL; VOLTAGE STABILIZING CIRCUITS;

ELECTRIC CURRENT REGULATORS;

EID: 70449492847     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2028919     Document Type: Article

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