A small-area voltage regulator with high-bandwidth supply-rejection using a regulated replica in 45nm CMOS SOI

Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

Volumn , Issue , 2008, Pages 157-160

  Toifl, Thomas ^a   Menolfi, Christian ^a   Buchmann, Peter ^a   Kossel, Marcel ^a   Morf, Thomas ^a   Schmatz, Martin ^a  

^a IBM RESEARCH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT SOURCE TRANSISTORS; HIGH BANDWIDTH; LOAD PATHS; LOOP STABILITY; LOW-DROPOUT VOLTAGE REGULATORS; POWER SUPPLY REJECTION; SMALL AREA; WIDE FREQUENCY RANGE;

ELECTRIC POTENTIAL; ELECTRIC POWER DISTRIBUTION; ELECTRIC POWER TRANSMISSION NETWORKS; ELECTRIC POWER UTILIZATION; VOLTAGE CONTROL; VOLTAGE STABILIZING CIRCUITS;

ELECTRIC CURRENT REGULATORS;

EID: 67649974018     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2008.4708752     Document Type: Conference Paper

References (3)

1. E. Alon, J. Kim, S. Pamarti, K. Chang, and M. Horowitz, "Replica compensated linear regulators for supply-regulated phase-locked loops," IEEE J. of Solid-State Circuits, vol. 41, pp. 413 - 424, February 2006.
2. G. W. den Besten, B. Nauta; Embedded 5 V-to-3.3 V voltage regulator for supplying digital IC's in 3.3 V CMOS technology, IEEE J. of Solid-State Circuits, vol. 33, pp. 956 - 962, July 1998.
3. J. G. Maneatis; Low-jitter process-independent DLL and PLL based on self-biased techniques, IEEE J. of Solid-State Circuits, vol. 31, pp. 1723 - 1732, November 1996.