An efficient approach for system-level timing simulation of compiler-optimized embedded software

Proceedings - Design Automation Conference

Volumn , Issue , 2009, Pages 220-225

  Wang, Zhonglei ^a   Herkersdorf, Andreas ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

Author keywords

iSciSim; Software timing simulation; System level design

Indexed keywords

BINARY CODES; COMPUTER AIDED DESIGN; COMPUTER PROGRAMMING LANGUAGES; PROGRAM COMPILERS; TIMING CIRCUITS;

EMBEDDED SYSTEM DEVELOPMENT; ISCISIM; LOW LEVEL REPRESENTATION; QUANTITATIVE COMPARISON; SOFTWARE PERFORMANCE ESTIMATIONS; STATE-OF-THE-ART APPROACH; SYSTEM LEVEL DESIGN; TIMING SIMULATIONS;

SYSTEMS ANALYSIS;

EID: 70350738611     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1629911.1629973     Document Type: Conference Paper

References (13)

1. J. R. Bammi, W. Kruijtzer, L. Lavagno, E. Harcourt, and M. Lazarescu. Software performance estimation strategies in a system-level design tool. In Proceedings of the International Workshop on HW/SW Codesign, 2000.
2. E. Cheung, H. Hsieh, and F. Balarin. Framework for fast and accurate performance simulation of multiprocessor systems. In Proceedings of IEEE International Workshop on High Level Design Validation and Test, 2007.
3. M.-K. Chung, S. Yang, S.-H. Lee, and C.-M. Kyung. System-level HW/SW co-simulation framework for multiprocessor and multithread SoC. In Proceedings of IEEE VLSI-TSA international symposium on VLSI Design, Automation and Test, 2005.
4. F. Fummi, G. Perbellini, M. Loghi, and M. Poncino. ISS-centric modular HW/SW co-simulation. In Proceedings of the ACM Great Lakes symposium on VLSI, 2006.
5. P. Giusto, G. Martin, and E. Harcourt. Reliable estimation of execution time of embedded software. In Proceedings of the conference on Design, Automation and Test in Europe, 2001.
6. T. Kempf, K. Karuri, S. Wallentowitz, G. Ascheid, R. Leupers, and H. Meyr. A SW performance estimation framework for early system-level-design using fine-grained instrumentation. In Proceedings of the conference on Design, Automation and Test in Europe, 2006.
7. M. Lazarescu, M. Lajolo, J. Bammi, E. Harcourt, and L. Lavagno. Compilation-based software performance estimation for system level design. In Proceedings of the International Workshop on HW/SW Codesign, 2000.
8. J.-Y. Lee and I.-C. Park. Timed compiled-code simulation of embedded software for performance analysis of SOC design. In Proceedings of the Design Automation Conference, 2002.
9. T. Meyerowitz, M. Sauermann, D. Langen, and A. Sangiovanni-Vincentelli. Source-level timing annotation and simulation for a heterogeneous multiprocessor. In Proceedings of the conference on Design, Automation and Test in Europe, 2008.
10. T. Nakada, T. Tsumura, and H. Nakashima. Design and implementation of a workload specific simulator. In Proceedings of the annual Symposium on Simulation, 2006.
11. J. Schnerr, O. Bringmann, A. Viehl, and W. Rosenstiel. High-performance timing simulation of embedded software. In Proceedings of the Design Automation Conference, 2008.
12. Z. Wang, A. Sanchez, and A. Herkersdorf. Scisim: A software performance estimation framework using source code instrumentation. In Proceedings of the International Workshop on Software and Performance, 2008.
13. V. Zivojnovic and H. Meyr. Compiled HW/SW co-simulation. In Proceedings of the Design Automation Conference, 1996.