Framework for fast and accurate performance simulation of multiprocessor systems

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn , Issue , 2007, Pages 21-28

  Cheung, Eric ^a   Hsieh, Harry ^a   Balarin, Felice ^b  

^a University of California Riverside   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FAULT TOLERANCE; MULTIPROCESSING SYSTEMS; QUALITY ASSURANCE; RELIABILITY; TESTING;

ACCURATE PERFORMANCE; CONCURRENT TASKS; HIGH LEVEL DESIGNS; INSTRUCTION-SET SIMULATOR (ISS); INTERMEDIATE REPRESENTATIONS; INTERNATIONAL (CO); MULTI PROCESSOR SYSTEMS; SIMULATION KERNELS; SIMULATION MODELLING; SIMULATION MODULES; SOFTWARE PROCESSING; SYSTEM DESIGNS; SYSTEM PERFORMANCE RESULTS; SYSTEMC;

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EID: 47949133696     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2007.4392780     Document Type: Conference Paper

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