Sequential optimization in the absence of global reset

ACM Transactions on Design Automation of Electronic Systems

Volumn 8, Issue 2, 2003, Pages 222-251

  Singhal, Vigyan ^a   Pixley, Carl ^b   Aziz, Adnan ^c   Qadeer, Shaz ^d   Brayton, Robert ^e  

^a Tempus Fugit Inc   (United States)

^b SYNOPSYS INC   (United States)

^c UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^d MICROSOFT   (United States)

^e UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

No reset latches; Safe replaceability; Sequential logic synthesis

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; COMPUTER AIDED DESIGN; FORMAL LOGIC;

LOGIC SYNTHESIS;

SEQUENTIAL CIRCUITS;

EID: 0037984743     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/762488.762493     Document Type: Review

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