-
1
-
-
0030403629
-
-
1996, pp. 346-353.
-
P. Ashar, A. Gupta, and S. Malik, "Using complete-1-distinguishability for FSM equivalence checking," in P roc. Int. Conf. Computer-Aided Design, 1996, pp. 346-353.
-
A. Gupta, and S. Malik, "Using Complete-1-distinguishability for FSM Equivalence Checking," in P Roc. Int. Conf. Computer-Aided Design
-
-
Ashar, P.1
-
3
-
-
0028413136
-
-
13, pp. 401-4124, Apr. 1994.
-
J.R. Burch et at., "Symbolic model checking for sequential circuit verification," IEEE Trans. Compute r-Aided Design, vol. 13, pp. 401-4124, Apr. 1994.
-
Et At., "Symbolic Model Checking for Sequential Circuit Verification," IEEE Trans. Compute R-Aided Design, Vol.
-
-
Burch, J.R.1
-
8
-
-
84856140605
-
-
407, pp. 365-373, 1989.
-
O. Coudert, C. Berthet, and J.C. Madre, "Verification of synchronous sequential machines based on symbolic execution," Proc. Workshop Automatic Verification Methods for Finite State Machines, vol. 407, pp. 365-373, 1989.
-
C. Berthet, and J.C. Madre, "Verification of Synchronous Sequential Machines Based on Symbolic Execution," Proc. Workshop Automatic Verification Methods for Finite State Machines, Vol.
-
-
Coudert, O.1
-
11
-
-
33749875783
-
-
1997.
-
C.A. J. van Eijk, "Formal methods for the verification of digital circuits," Ph.D. dissertation, Eindhoven Univ. Technol., Eindhoven, The Netherlands, Sept. 1997.
-
Van Eijk, "Formal Methods for the Verification of Digital Circuits," Ph.D. Dissertation, Eindhoven Univ. Technol., Eindhoven, the Netherlands, Sept.
-
-
-
12
-
-
33749971191
-
-
1992.
-
T. Filkorn, "Symbolische methoden für die Verifikation endlicher zustandssysteme," Ph.D. dissertation, Institut für Informatik der Technischen Universität München, Munich, Germany, 1992.
-
"Symbolische Methoden Für Die Verifikation Endlicher Zustandssysteme," Ph.D. Dissertation, Institut Für Informatik Der Technischen Universität München, Munich, Germany
-
-
Filkorn, T.1
-
14
-
-
0029695303
-
-
1996, pp. 277-281.
-
S.-Y. Huang, K.-T. Cheng, and K.-C. Chen, "On verifying the correctness of retimed circuits," in Proc. Great Lakes Symp. VLSI, 1996, pp. 277-281.
-
K.-T. Cheng, and K.-C. Chen, "On Verifying the Correctness of Retimed Circuits," in Proc. Great Lakes Symp. VLSI
-
-
Huang, S.-Y.1
-
15
-
-
0030651916
-
-
1997, pp. 455-4160.
-
S.-Y. Huang, K.-T. Cheng, and K.-C. Chen, "AQUILA: An equivalence verifier for large sequential circuits," in Proc. Asian South Pacific Design Automation Conf., 1997, pp. 455-4160.
-
K.-T. Cheng, and K.-C. Chen, "AQUILA: an Equivalence Verifier for Large Sequential Circuits," in Proc. Asian South Pacific Design Automation Conf.
-
-
Huang, S.-Y.1
-
16
-
-
0029225168
-
-
32nd Design Automation Conf., 1995, pp. 420-426.
-
J. Jain, R. Mukherjee, and M. Fujita, "Advanced verification techniques based on learning," in Proc. 32nd Design Automation Conf., 1995, pp. 420-426.
-
R. Mukherjee, and M. Fujita, "Advanced Verification Techniques Based on Learning," in Proc.
-
-
Jain, J.1
-
21
-
-
0030385994
-
-
1996, pp. 88-95.
-
D.K. Pradhan, D. Paul, and M. Chatterjee, "VERILAT: Verification using logic augmentation and transformations," in Proc. Int. Conf. Computer-Aided Design, 1996, pp. 88-95.
-
D. Paul, and M. Chatterjee, "VERILAT: Verification Using Logic Augmentation and Transformations," in Proc. Int. Conf. Computer-Aided Design
-
-
Pradhan, D.K.1
-
23
-
-
84893615994
-
-
1999, pp. 138-144.
-
R.K. Ranjan et al., "Using combinational verification for sequential circuits," in Proc. Design, Automation Test Europe Conf., 1999, pp. 138-144.
-
Et Al., "Using Combinational Verification for Sequential Circuits," in Proc. Design, Automation Test Europe Conf.
-
-
Ranjan, R.K.1
-
24
-
-
51549106001
-
-
1995, pp. 150-154.
-
L. Stok, I. Spillinger, and G. Even, "Improving initialization through reversed retiming," in Proc. Eur. Design Test Conf., 1995, pp. 150-154.
-
I. Spillinger, and G. Even, "Improving Initialization through Reversed Retiming," in Proc. Eur. Design Test Conf.
-
-
Stok, L.1
|