Hardware-software partitioning for embedded multiprocessor FPGA systems

International Journal of Innovative Computing, Information and Control

Volumn 5, Issue 10, 2009, Pages 3071-3083

  Lee, Trong Yen ^a   Fan, Yang Hsin ^a,b   Cheng, Yu Min ^a   Tsai, Chia Chun ^c  

^a NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY   (Taiwan)

^b NATIONAL TAITUNG UNIVERSITY   (Taiwan)

^c NANHUA UNIVERSITY   (Taiwan)

Author keywords

Embedded multiprocessor; FPGA system; Genetic algorithm; Hardware oriented partitioning; Hardware software partitioning

Indexed keywords

EMBEDDED MULTIPROCESSOR; EMBEDDED MULTIPROCESSORS; EXECUTION TIME; FPGA SYSTEM; HARDWARE-SOFTWARE PARTITIONING; MEMORY SIZE; SOFTWARE PARTITIONS; SYSTEM CONSTRAINTS;

EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); GENETIC ALGORITHMS; HARDWARE; MULTIPROCESSING SYSTEMS;

EMBEDDED SOFTWARE;

EID: 70350500720     PISSN: 13494198     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (28)

1. Xilinx website, http://www.xilinx.com/
2. G. F. Marchioro, J. M. Daveau and A. A. Jerraya, Transformational partitioning for co-design of multiprocessor systems, Proc. of the IEEE Conf. on Computer Aided Design, pp. 508-515, 1997.
3. M. Srivastava and R. Brodersen, SIERA: A unified framework for rapid-prototyping of systemlevel hardware and software, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 676-693, 1995.
4. W. Wolf, A decade of hardware/software codesign, IEEE Computer, vol. 36, no. 4, pp. 38-43, 2003.
5. R. Ernst, Codesign of embedded systems: Status and trends, IEEE Design and Test of Computers, vol. 15, no. 2, pp. 45-54, 1998.
6. N. S. Woo, A. E. Dunlop and W. Wolf, Codesign from cospecification, IEEE Computer, vol. 27, pp. 42-47, 1994.
7. R. K. Gupta and G. D. Micheli, System synthesis via hardware-software co-design, Technical Report No. CSL-TR-92-548, Computer System Laboratory, Standford Univ., pp. 1247-1263, 1993.
8. R. K. Gupta, N. C. Claudionor and G. De Micheli, Program implementation schemes for hardwaresoftware systems, IEEE Computer, vol. 27, no. 1, pp. 48-55, 1994.
9. C. J. N. C. Jr, D. C. D. S. Jr and A. O. Fernandes, Hardware-software codesign of embedded systems, Proc. of the XI Brazilian Symposium on Integrated Circuit Design, pp. 2-8, 1998.
10. R. Ernst, J. Henkel and T. Benner, Hardware-software cosynthesis for microcontrollers, IEEE Design & Test of Computer, vol. 10, pp. 64-75, 1993.
11. V. Srinivasan, S. Govindarajan and R. Vemuri, Fine-grained and coarse-grained behavioral partitioning with effective utilization of memory and design space exploration for multi-fpga architectures, IEEE Trans. on Very Large Scale Integration Systems, vol. 9, pp. 140-158, 2001.
12. D. Saha, R. S. Mitra and A. Basu, Hardware software partitioning using genetic algorithm, Proc. of the 10th Conf. on VLSI Design, pp. 155-160, 1997.
13. Y. Zou, Z. Zhuang and H. Cheng, HW-SW partitioning based on Genetic algorithm, Proc. of the Congress on Evolutionary Computation, vol. 1, pp. 628-633, 2004.
14. H. Kanoh, M. Matsumoto and S. Nishihar, Genetic algorithms for constraint satisfaction problems, Proc. of the IEEE Conf. on Man and Cybernetics Systems, vol. 1, pp. 626-631, 1995.
15. A. L. Buczak and H. Wang, Optimization of fitness functions with non-ordered parameters by genetic algorithms, Proc. of the Conf. on Evolutionary Computation Congress, vol. 1, pp. 199-206, 2001.
16. K. Deb and S. Agrawal, Understanding Interactions among Genetic Algorithm Parameters: Foundations of Genetic Algortihms 5, Morgan Kaufmann Publishers, San Francisco, CA, 1999.
17. S. Palaniappan, S. Zein-Sabatto and A. Sekmen, Dynamic multi-objective optimization of war resource allocation using adaptive genetic algorithms, Proc. of the IEEE Conf. on Southeast Congress, pp. 160-165, 2001.
18. T. Y. Lee, P. A. Hsiung and S. J. Chen, Hardware-software multi-level partitioning for distributed embedded multiprocessor systems, IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, pp. 614-626, 2001.
19. L. Pomante, Co-design of multiprocessor embedded systems: An heuristic multi-level partitioning methodology, Proc. of the IFIP Conf. on Chip Design Automation, pp. 421-425, 2000.
20. C. Brandolese, W. Fornaciari, L. Pomante, F. Salice and D. Sciuto, Affinity-driven system design exploration for heteregenerous multiprocessor SoC, IEEE Trans. on Computer, vol. 55, no. 5, pp. 508519, 2006.
21. D. Sciuto, F. Salice, L. Pomante and W. Fornaciari, Metrics for design space exploration of heterogeneous multiprocessor embedded systems, Proc. of the Conf. on IEEE/ACM Hardware Software Co-Design, pp. 55-60, 2002.
22. T. Y. Lin, Y. T. Hung and R. G. Chang, Efficient hardware/software partitioning approach for embedded multiprocessor systems, Proc. of the Conf. on VLSI Design, Automation and Test Symposium, pp. 231-234, 2006.
23. C. C. Chang, C. C. Lin and Y. S. Hu, An SVD oriented watermark embedding scheme with high qualities for the restored images, International Journal of Innovative Computing, Information and Control, vol. 3, no. 3, pp. 609-620, 2007.
24. L. Mi and F. Takeda, Analysis on the robustness of the pressure-based individual identification system based on neural networks, International Journal of Innovative Computing, Information and Control, vol. 3, no. 1, pp. 97-110, 2007.
25. A. Fekih, H. Xu and F. Chowdhury, Neural networks based system identification techniques for model based fault detection of nonlinear systems, International Journal of Innovative Computing, Information and Control, vol. 3, no. 5, pp. 1073-1085, 2007.
26. G. K. Wallace, The JPEG still picture compression standard, IEEE Trans. on Consumer Electronics, vol. 38, pp.xviii-xxxiv, 1992.
27. K. Kim and J. J. Koh, An area efficient DCT architecture for MPEG-2 video encoder, IEEE Trans. on Consumer Electronics, vol. 45, pp. 62-67, 1999.
28. T. Y. Lee, Y. H. Fan, Y. M. Cheng, C. C. Tsai and R. S. Hsiao, Hardware-oriented partition for embedded multiprocessor FPGA systems, Proc. of the IEEE Conf. on Innovative Computing, Information and Control, 2007.