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Volumn 45, Issue 1, 1999, Pages 62-67

An area efficient dct architecture for MPEG-2 video encoder

(2)  Kim, Kyeounsoo a   Koh, Jong Seog a  

a NONE

Author keywords

Discrete cosine transform; Mpeg 2 video encoder; Transform coding

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; COSINE TRANSFORMS; DIGITAL ARITHMETIC; DIGITAL IMAGE STORAGE; IMAGE COMPRESSION; MATRIX ALGEBRA; MULTIMEDIA SYSTEMS; TWO DIMENSIONAL; VIDEO SIGNAL PROCESSING; VLSI CIRCUITS;

EID: 0032664920     PISSN: 00983063     EISSN: None     Source Type: Journal    
DOI: 10.1109/30.754418     Document Type: Article
Times cited : (24)

References (10)
  • 4
    • 0024646951 scopus 로고    scopus 로고
    • 16x16 Discrete Cosine Transform Chip", IEEE Trans. Circuits and Syst., pp. 610-617, April 1989.
    • M. T. Sun, T. C. Chen, and A. M. Gottlieb, "VLSI Implementation of a 16x16 Discrete Cosine Transform Chip", IEEE Trans. Circuits and Syst., pp. 610-617, April 1989.
    • T. C. Chen, and A. M. Gottlieb, "VLSI Implementation of a
    • Sun, M.T.1
  • 5
    • 0026854652 scopus 로고    scopus 로고
    • 100-MHz 2-D Discrete Cosine Transform Core Processor", IEEE .7. of Solid-State Circuits, Vol.27;No.4, pp. 492-499, April 1992.
    • I. Uramoto et al., "A 100-MHz 2-D Discrete Cosine Transform Core Processor", IEEE .7. of Solid-State Circuits, Vol.27;No.4, pp. 492-499, April 1992.
    • "A
    • Uramoto, I.1
  • 6
    • 0029292227 scopus 로고    scopus 로고
    • 100 MHz 2-D DCT/IDCT Processor for HDTV Applications", IEEE Trans. CAS for Video Tech., Vol.5,No.2, pp. 158-165, April 1995.
    • A. Madisetti et al., "A 100 MHz 2-D DCT/IDCT Processor for HDTV Applications", IEEE Trans. CAS for Video Tech., Vol.5,No.2, pp. 158-165, April 1995.
    • "A
    • Madisetti, A.1
  • 9
    • 33748183092 scopus 로고    scopus 로고
    • 1996.
    • ISO/IEC JTC1/SC29/WG11 13818-2 : Moving Picture Experts Group, IS, May 1996.
    • IS, May
    • Group, M.P.E.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.