-
1
-
-
84881201983
-
-
The MathWorks
-
The MathWorks, "Simulink," www.mathworks.com/.
-
Simulink
-
-
-
2
-
-
49749117244
-
-
Online, Available:, www.forteds.com/products/cynthesizer.asp
-
Forte Design Systems, "Cynthesizer," www.forteds.com. [Online]. Available: http://www.forteds.com/products/cynthesizer.asp
-
Cynthesizer
-
-
Design Systems, F.1
-
3
-
-
70350048971
-
-
Synfora, "Pico Express," www.synfora.com.
-
Pico Express
-
-
-
4
-
-
20344377909
-
Evaluating heuristics in automatically mapping multi-loop applications to FPGAs
-
H. Ziegler and M. Hall, "Evaluating heuristics in automatically mapping multi-loop applications to FPGAs," in FPGA, 2005, pp. 184-195.
-
(2005)
FPGA
, pp. 184-195
-
-
Ziegler, H.1
Hall, M.2
-
5
-
-
33750334716
-
Scalable and structured scheduling
-
P. Feautrier, "Scalable and structured scheduling," Int. J. Parallel Program., vol. 34, pp. 459-487, 2006.
-
(2006)
Int. J. Parallel Program
, vol.34
, pp. 459-487
-
-
Feautrier, P.1
-
6
-
-
33847655159
-
Nonlinear diffusion in laplacian pyramid domain for ultrasonic speckle reduction
-
F. Zhang, Y. M. Yoo, L. M. Koh, and Y. Kim, "Nonlinear diffusion in laplacian pyramid domain for ultrasonic speckle reduction," IEEE Trans. Med. Imaging, vol. 26, pp. 200-211, 2007.
-
(2007)
IEEE Trans. Med. Imaging
, vol.26
, pp. 200-211
-
-
Zhang, F.1
Yoo, Y.M.2
Koh, L.M.3
Kim, Y.4
-
7
-
-
34547476023
-
A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing
-
Sep
-
H. Dutta, F. Hannig, J. Teich, B. Heigl, and H. Hornegger, "A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing," in Proceedings of IEEE 17th International Conference on Application-specific Systems, Architectures, and Processors (ASAP), Sep. 2006, pp. 331-337.
-
(2006)
Proceedings of IEEE 17th International Conference on Application-specific Systems, Architectures, and Processors (ASAP)
, pp. 331-337
-
-
Dutta, H.1
Hannig, F.2
Teich, J.3
Heigl, B.4
Hornegger, H.5
-
8
-
-
34347362802
-
Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs
-
S. Stuijk, M. Geilen, and T. Basten, "Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs," in DAC, 2006, pp. 899-904.
-
(2006)
DAC
, pp. 899-904
-
-
Stuijk, S.1
Geilen, M.2
Basten, T.3
-
9
-
-
34548014921
-
-
University of Twente, Tech. Rep, Nov
-
M. Wiggers, M. Bekooij, and G. Smit, "Efficient computation of buffer capacities for cyclostatic dataflow graphs," University of Twente, Tech. Rep., Nov. 2006.
-
(2006)
Efficient computation of buffer capacities for cyclostatic dataflow graphs
-
-
Wiggers, M.1
Bekooij, M.2
Smit, G.3
-
10
-
-
0032648555
-
Synthesis of embedded software from synchronous dataflow specifications
-
S. S. Bhattacharyya, P. K. Murthy, and E. A. Lee, "Synthesis of embedded software from synchronous dataflow specifications," J. of VLSI Signal Processing Systems, vol. 21, pp. 151-166, 1999.
-
(1999)
J. of VLSI Signal Processing Systems
, vol.21
, pp. 151-166
-
-
Bhattacharyya, S.S.1
Murthy, P.K.2
Lee, E.A.3
-
11
-
-
34548312056
-
Fast memory footprint estimation based on maximal dependency vector calculation
-
Q. Hu, A. Vandecappelle, P. G. Kjeldsberg, F. Catthoor, and M. Palkovic, "Fast memory footprint estimation based on maximal dependency vector calculation," in DATE, 2007, pp. 379-384.
-
(2007)
DATE
, pp. 379-384
-
-
Hu, Q.1
Vandecappelle, A.2
Kjeldsberg, P.G.3
Catthoor, F.4
Palkovic, M.5
-
12
-
-
34547453716
-
Loop transformation methodologies for array-oriented memory management
-
F. Balasa, P. G. Kjeldsberg, M. Palkovic, A. Vandecappelle, and F. Catthoor, "Loop transformation methodologies for array-oriented memory management," in ASAP, 2006, pp. 205-212.
-
(2006)
ASAP
, pp. 205-212
-
-
Balasa, F.1
Kjeldsberg, P.G.2
Palkovic, M.3
Vandecappelle, A.4
Catthoor, F.5
-
13
-
-
27444447639
-
Lattice-based memory allocation
-
A. Darte, R. Schreiber, and G. Villard, "Lattice-based memory allocation," IEEE Trans. on Comp., vol. 54, pp. 1242-1257, 2005.
-
(2005)
IEEE Trans. on Comp
, vol.54
, pp. 1242-1257
-
-
Darte, A.1
Schreiber, R.2
Villard, G.3
-
14
-
-
39749086249
-
Systematic and automated multiprocessor system design, programming, and implementation
-
H. Nikolov, T. Stefanov, and E. Deprettere, "Systematic and automated multiprocessor system design, programming, and implementation," IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 27, pp. 542-555, 2008.
-
(2008)
IEEE Trans. on CAD of Integrated Circuits and Systems
, vol.27
, pp. 542-555
-
-
Nikolov, H.1
Stefanov, T.2
Deprettere, E.3
-
15
-
-
11244312199
-
Modeling and scheduling parallel data flow systems using structured systems of recurrence equations
-
F. Charot, M. Nyamsi, P. Quinton, and C. Wagner, "Modeling and scheduling parallel data flow systems using structured systems of recurrence equations," in ASAP, 2004, pp. 6-16.
-
(2004)
ASAP
, pp. 6-16
-
-
Charot, F.1
Nyamsi, M.2
Quinton, P.3
Wagner, C.4
-
16
-
-
34548789474
-
C++ based system synthesis of real-time video processing systems targeting FPGA implementation
-
N. Lawal, M. O'Nils, and B. Thörnberg, "C++ based system synthesis of real-time video processing systems targeting FPGA implementation," in IPDPS, 2007, pp. 1-7.
-
(2007)
IPDPS
, pp. 1-7
-
-
Lawal, N.1
O'Nils, M.2
Thörnberg, B.3
-
17
-
-
33947613533
-
Modeling and analysis of windowed synchronous algorithms
-
J. Keinert, C. Haubelt, and J. Teich, "Modeling and analysis of windowed synchronous algorithms," ICASSP, vol. III, pp. 892-895, 2006.
-
(2006)
ICASSP
, vol.3
, pp. 892-895
-
-
Keinert, J.1
Haubelt, C.2
Teich, J.3
-
18
-
-
47849126837
-
Multidimensional incremental loop fusion for data locality
-
S. Verdoolaege, M. Bruynooghe, G. Janssens, and F. Catthoor, "Multidimensional incremental loop fusion for data locality," ASAP, pp. 17-27, 2003.
-
(2003)
ASAP
, pp. 17-27
-
-
Verdoolaege, S.1
Bruynooghe, M.2
Janssens, G.3
Catthoor, F.4
|