메뉴 건너뛰기




Volumn , Issue , 2006, Pages 331-337

A design methodology for hardware acceleration of adaptive filter algorithms in image processing

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; MAPPING; MEDICAL IMAGING; PARALLEL PROCESSING SYSTEMS;

EID: 34547476023     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2006.4     Document Type: Conference Paper
Times cited : (26)

References (13)
  • 2
    • 33745600592 scopus 로고    scopus 로고
    • Interfacing compiled FPGA programs: The MMAlpha approach
    • S. Derrien and T. Risset. Interfacing compiled FPGA programs: the MMAlpha approach. In PDPTA, 2000.
    • (2000) PDPTA
    • Derrien, S.1    Risset, T.2
  • 4
    • 0041374022 scopus 로고    scopus 로고
    • A Nonlinear Multi-resolution Gradient-Adaptive Filter for Medical Images
    • Feb
    • D. Kunz, K. Eck, H. Fillbrandt, and T. Aach. A Nonlinear Multi-resolution Gradient-Adaptive Filter for Medical Images. SPIE Medical Imaging, SPIE, 5032:732-742, Feb. 2003.
    • (2003) SPIE Medical Imaging, SPIE , vol.5032 , pp. 732-742
    • Kunz, D.1    Eck, K.2    Fillbrandt, H.3    Aach, T.4
  • 5
    • 85029516676 scopus 로고
    • Loop Parallelization in the Polytope Model
    • E. Best, editor, CONCUR'93, Springer-Verlag
    • C. Lengauer. Loop Parallelization in the Polytope Model. In E. Best, editor, CONCUR'93, Lecture Notes in Computer Science 715, pages 398-416. Springer-Verlag, 1993.
    • (1993) Lecture Notes in Computer Science , vol.715 , pp. 398-416
    • Lengauer, C.1
  • 6
    • 0035251545 scopus 로고    scopus 로고
    • VLSI Design Methodoloy for Edge-preserving Image Reconstruction
    • February
    • E. Mémin and T. Risset. VLSI Design Methodoloy for Edge-preserving Image Reconstruction. Real Time Imaging, 7(1):109-126, February 2001.
    • (2001) Real Time Imaging , vol.7 , Issue.1 , pp. 109-126
    • Mémin, E.1    Risset, T.2
  • 8
    • 34547424319 scopus 로고    scopus 로고
    • PARO Design System Project
    • PARO Design System Project, www12.cs.fau.de/research/paro.
  • 9
    • 26444524332 scopus 로고    scopus 로고
    • H. Ruckdeschel, H. Dutta, F. Hannig, and J. Teich. Automatic FIR Filter Generation for FPGAs. In T. Hämäläinen, A. Pimentel, J. Takala, and S. Vassiliadis, editors, Embedded Computer Systems: Architectures, Modeling, and Simulation, 5th International Workshop, SAMOS 2005, Proceedings, 3553 of Lecture Notes in Computer Science (LNCS), pages 51-61, Island of Samos, Greece, July 2005. Springer.
    • H. Ruckdeschel, H. Dutta, F. Hannig, and J. Teich. Automatic FIR Filter Generation for FPGAs. In T. Hämäläinen, A. Pimentel, J. Takala, and S. Vassiliadis, editors, Embedded Computer Systems: Architectures, Modeling, and Simulation, 5th International Workshop, SAMOS 2005, Proceedings, volume 3553 of Lecture Notes in Computer Science (LNCS), pages 51-61, Island of Samos, Greece, July 2005. Springer.
  • 10
    • 34547456972 scopus 로고    scopus 로고
    • Synfora, Inc
    • Synfora, Inc. www.synfora.com.
  • 11
    • 0006436941 scopus 로고
    • PhD thesis, Institut für Mikroelektronik, Universität des Saarlandes, Saarbrücken, Germany, September
    • J. Teich. A Compiler for Application-Specific Processor Arrays. PhD thesis, Institut für Mikroelektronik, Universität des Saarlandes, Saarbrücken, Germany, September 1993.
    • (1993) A Compiler for Application-Specific Processor Arrays
    • Teich, J.1
  • 12
    • 0031221084 scopus 로고    scopus 로고
    • Scheduling of Partitioned Regular Algorithms on Processor Arrays with Constrained Resources
    • Sept
    • J. Teich, L. Thiele, and L. Zhang. Scheduling of Partitioned Regular Algorithms on Processor Arrays with Constrained Resources. Journal of VLSI Signal Processing, 17(1):5-20, Sept. 1997.
    • (1997) Journal of VLSI Signal Processing , vol.17 , Issue.1 , pp. 5-20
    • Teich, J.1    Thiele, L.2    Zhang, L.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.