Modeling and scheduling parallel data flow systems using structured systems of recurrence equations

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2004, Pages 6-16

  Charot, François ^a   Nyamsi, Madeleine ^a   Quinton, Patrice ^a   Wagner, Charles ^a  

^a CAMPUS DE BEAULIEU   (France)

Author keywords

3G mobile telephony; Data flow systems; FPGA; Multi rate systems; Prototyping; Scheduling; Systems of recurrence equations; WCDMA

Indexed keywords

CODE DIVISION MULTIPLE ACCESS; COMPUTER ARCHITECTURE; FIELD PROGRAMMABLE GATE ARRAYS; FORMAL LANGUAGES; HIERARCHICAL SYSTEMS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; MULTIMEDIA SYSTEMS; SOFTWARE PROTOTYPING; SYNCHRONOUS MACHINERY; TELECOMMUNICATION SYSTEMS;

3G MOBILE TELEPHONY; DATA FLOW SYSTEMS; MULTI-RATE SYSTEMS; PROTOTYPING; SYSTEM OF RECURRENCE EQUATIONS; WCDMA;

DATA FLOW ANALYSIS;

EID: 11244312199     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

1. Chamski, Z. and Cohen, A. and Duranton, M. and Eisenbeis, C. and Feautrier, P. and Genius, D. and Pasquier, L. and Rivierre-Vier, V. The SANDRA Project: Cooperative Architecture/Compiler Technology for Embedded Real-Time Streaming Applications. Research Report RR-4773, INRIA, Mar. 2003.
2. F. Charot, M. Nyamsi, P. Quinton, and C. Wagner. Architecture Exploration for 3G Telephony Applications Using a Hardware-Software Prototyping Platform. In Proceedings of Samoa IV Workshop, Samos, Greece, July 2004.
3. Cohen, A. and Genius, D. and Kortebi, A. and Chamski, Z. and Duranton, M. Multi-Periodic Process Networks: Technical Report. Research Report RR-4496, INRIA, July 2002.
4. A. O. Dahmane and D. Massicotte. Wideband CDMA Receivers for 3G Wireless Communications: Algorithm and Implementation Study. In IASTED Wireless and Optical Communication, July 17-19 2002.
5. H. Holma and A. Toskala. WCDMA for UMTS: Radio Access For Third Generation Mobile Communication. John Wiley & Son, second edition, 2002.
6. K. Ito and K. K. Parhi. Determining the Minimum Iteration Period of an Algorithm. Journal of VLSI Signal Processing, 11:229-244, 1995.
7. B. Kienhuis, E. Rijpkema, and E. Deprettere. Compaan: Deriving Process Networks from Matlab for Embedded Signal Processing Architectures. In Proceedings of the 8th International Workshop on Hardware/Software Codesign (CODES-00), pages 13-17, NY, May 3-5 2000. ACM.
8. Le Verge, C. Mauras, and P. Quint on. The ALPHA Language and its Use for the Design of Systolic Arrays. Journal of VLSI Signal Processing, 3:173-182, 1991.
9. E. Lee and D. Messerchmitt. Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing. IEEE Transactions of Computers, C-36(1), Jan. 1987. Synchronous data-flow.
10. E. A. Lee and A. Sangiovanni-Vincentelli. Comparing Models of Computation. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pages 234-243, Washington, Nov. 10-14 1996. IEEE Computer Society Press.
11. N. D. P. M. Lenders and S. Rajopadhye. Multirate and Sparse Systolic Architectures. In Australasian Computer Architecture Conference, Melbourne, Australia, pages 67-78. Springer-Verlag, Singapore, Jan. 1996.
12. D. Menard, M. Guitton, S. Pillement, and O. Sentieys. Design and Implementation of WCDMA Platforms: Challenges and Trade-offs. In International Signal Processing Conference (ISPC'03), Dallas, US, Apr. 2003.
13. A. Mozipo, D. Massicotte, P. Quinton, and T. Risset. A Parallel Architecture for Adaptative Channel Equalization Based On Kalman Filter Using MMAlpha. 1999 IEEE Canadian Conference on Electrical & Computer Engineering, pages 554-559, May 1999.
14. P. K. Murthy and E. A. Lee. Multidimensional Synchronous Dataflow. IEEE Tr on Signal Processing, 50(7):2064-2079, 2002.
15. P. Quinton and T. Risset. Structured Scheduling of Recurrence Equations: Theory and Practice. In Proc. of the System Architecture Modelling and Simulation Workshop, Lecture Notes in Computer Science, Samos, Greece, 2001. Springer Verlag.
16. P. Quinton and Y. Robert. Systolic Algorithms and Architectures. Prentice Hall and Masson, 1989.
17. S. Rajagopal, S. Bhashyam, J. Cavallaro, and B. Aazhang. Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-Station Receivers. Journal of VLSI Signal Processing, 31(2):143-156, June 2002.
18. S. Verdu. Multiuser Detection. Cambridge University Press, 1998.