Enabling concurrent clock and power gating in an industrial design flow

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2009, Pages 334-339

  Bolzani, Leticia ^a   Calimera, Andrea ^a   Macii, Alberto ^a   Macii, Enrico ^a   Poncino, Massimo ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

PRODUCT DESIGN; TRANSISTORS;

65NM CMOS TECHNOLOGY; CONTROL SIGNAL; EFFECTIVE SOLUTION; LEAKAGE MINIMIZATION; NUMBER OF CLUSTERS; RUNTIME LEAKAGE; SLEEP TRANSISTORS; SYNTHESIS TOOL;

CLOCKS;

EID: 70350048948     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2009.5090684     Document Type: Conference Paper

References (10)

1. L. Benini, P. Siegel, G. De Micheli, "Automatic Synthesis of Gated Clocks for Power Reduction in Sequential Circuits," IEEE Design and Test of Computers, Vol. 11, No. 4, pp. 32-40, 1994.
2. L. Benini, G. De Micheli, "Transformation and Synthesis of FSMs for Low Power Gated Clock Implementation," IEEE Transactions on CAD, Vol. 15, No. 6, pp. 630-643, 1996.
3. L. Benini, G. De Micheli, E. Macii, M. Poncino, R. Scarsi, "Symbolic Synthesis of Clock-Gating Logic for Power Optimization of Synchronous Controllers," ACM Transactions on Design Automation, Vol. 4, No. 4, pp. 351-375, 1999.
4. P. Babighian, L. Benini, E. Macii, "A Scalable Algorithm for RTL Insertion of Gated Clocks based on Observability Don't Cares Computation," IEEE Transactions on CAD, Vol. 24, No. 1, pp. 29-42, 2005.
5. M. Anis, S. Areibi, M. Elmasry, "Design and Optimization of Multithreshold CMOS Circuits," IEEE Transactions on CAD, Vol. 22, No. 10, pp. 1324-1342, 2003.
6. C. Long, L. He, "Distributed Sleep Transistor Network for Power Reduction," DAC-41: ACM/IEEE Design Automation Conference, pp. 181-186, June 2003.
7. P. Babighian, L. Benini, E. Macii, A. Remollino, "Post-Layout Leakage Power Minimization Based on Distributed Sleep Transistor Insertion," ISLPED-04: ACM/IEEE International Symposium on Low Power Electronics and Design, pp. 138-143, August 2004.
8. A. Sathanur, A. Pullini, L. Benini, A. Macii, E. Macii, M. Poncino, "Timing-Driven Row-Based Power Gating," ISLPED-07: ACM/IEEE International Symposium on Low Power Electronics and Design, pp. 104-109, August 2007.
9. L. Bolzani, A. Calimera, A. Macii, E. Macii, M. Poncino, "Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits", DSD08: IEEE 11th Euromicro Conference on Digital System Design, September 2008, pp. 298-303.
10. K. Usami, N. Ohkubo, "A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals", ICCD-06: IEEE International Conference on Computer Design, pp. 155-161, October 2006.