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Volumn , Issue , 2009, Pages

High frequency characterization and modeling of high density TSV in 3D integrated circuits

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATED CIRCUIT; HIGH DENSITY; HIGH-FREQUENCY CHARACTERIZATION; MATERIAL CHARACTERISTICS; THROUGH SILICON VIAS; WAFER THINNING;

EID: 70350000414     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SPI.2009.5089840     Document Type: Conference Paper
Times cited : (61)

References (7)
  • 1
    • 70349978568 scopus 로고    scopus 로고
    • International Technology Roadmap for Semiconductors 2008 Ed. , http://www.itrs.net
    • International Technology Roadmap for Semiconductors 2008 Ed. , http://www.itrs.net
  • 3
    • 24344491536 scopus 로고    scopus 로고
    • Microwave Characterization and Modeling of High Aspect Ratio Through-Wafer Interconnect Vias in Silicon Substrates
    • August
    • Lydia Lap Wai Leung, "Microwave Characterization and Modeling of High Aspect Ratio Through-Wafer Interconnect Vias in Silicon Substrates," IEEE Trans on Microwave Theory and Techniques, vol. 53, no. 8,pp 2472-2480 August 2005.
    • (2005) IEEE Trans on Microwave Theory and Techniques , vol.53 , Issue.8 , pp. 2472-2480
    • Lap, L.1    Leung, W.2
  • 4
    • 42549142869 scopus 로고    scopus 로고
    • High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging
    • Dresden, Germany
    • Chunghyun Ryun and al , "High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging," 2006 Electronics System integration Technology Conference, Dresden, Germany.
    • 2006 Electronics System integration Technology Conference
    • Ryun, C.1    and al2
  • 5
    • 49049102928 scopus 로고    scopus 로고
    • Enabling technologies for 3D chip stacking,
    • April, VLSI-TSA, pp
    • P. Leduc et al, "Enabling technologies for 3D chip stacking, " VLSI Technology, Systems and Applications, April 2008. VLSI-TSA, pp 76-78 (2008)
    • (2008) VLSI Technology, Systems and Applications , pp. 76-78
    • Leduc, P.1
  • 6
    • 0035307256 scopus 로고    scopus 로고
    • Improved three-step de-embedding method to accurately account for the influence of pad parasitics in silicon on-wafer RF test-structures
    • April
    • E. W. Vandamme, D M. M.-P. Schreurs, C. van Dinther, "Improved three-step de-embedding method to accurately account for the influence of pad parasitics in silicon on-wafer RF test-structures," IEEE Trans. on electron devices, vol. 48, no 4, pp. 737-742, April 2001.
    • (2001) IEEE Trans. on electron devices , vol.48 , Issue.4 , pp. 737-742
    • Vandamme, E.W.1    Schreurs, D.M.M.-P.2    van Dinther, C.3
  • 7
    • 35348919396 scopus 로고    scopus 로고
    • Development and Evaluation of 3D Sip with Vertically Interconnected Through Silicon Vias (TSV)
    • Dong Min Jang, et al, "Development and Evaluation of 3D Sip with Vertically Interconnected Through Silicon Vias (TSV)," IEEE Electronic Components and Technology Conference 2007
    • IEEE Electronic Components and Technology Conference 2007
    • Dong, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.