High aspect ratio vias first for advanced packaging

Proceedings of the Electronic Packaging Technology Conference, EPTC

Volumn , Issue , 2007, Pages 215-221

  Henry, D ^a   Baillin, X ^a   Lapras, V ^a   Sillon, N ^a   Dunne, B ^b   Hernandez, C ^b   Vigier Blanc, E ^b  

^a CEA LETI   (France)

^b STMICROELECTRONICS   (France)

Author keywords

3D integration; Backside technology; Doped polysilicon filling; DRIE; Electrical resistance; High aspect ratio trenches; Via first

Indexed keywords

ELECTRONIC EQUIPMENT MANUFACTURE; ELECTRONICS PACKAGING; NONMETALS; PACKAGING; PHOTORESISTS; POLYSILICON; PRESSURE DROP; SILICON; SILICON WAFERS; TECHNOLOGY; WAFER BONDING;

3D INTEGRATION; ACTIVE DEVICES; ADVANCED PACKAGING; BACKSIDE TECHNOLOGY; DOPED POLYSILICON FILLING; DRIE; ELECTRICAL MEASUREMENTS; ELECTRICAL RESISTANCE; ELECTRICAL RESULTS; HIGH ASPECT RATIO; HIGH ASPECT RATIO TRENCHES; HIGH TEMPERATURE; PACKAGING TECHNOLOGIES; VIA FIRST; WAFER CARRIER;

ASPECT RATIO;

EID: 50049125339     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2007.4469792     Document Type: Conference Paper

References (14)

1. Rao R. Tummala et Al - "High density packaging in 2010 and beyond" - 2002 International Symposium on Electronic Materials and packaging - IEEE - pp 30-36.
2. Rao R. Tummala - "SOP: What is it and why? A new Microsystems-Integration Technology Paradigm-Moore's Law for system integration of miniaturized convergent systems of the next decade" - IEEE Transactions On advanced Packaging - Vol 27, No 2, may 2004 - pp 241-249
3. N. Sillon et Al - "Innovative flip chip solution for System on Wafer concept" - 3 S workshop - September 2005 -Atlanta.
4. D. Henry et Al - "Through vias technology for System on wafer approach" - ENCAST Workshop Zurich - 08 & 09 november 2005.
5. K. Takahashi et Al - " Process integration of 3D Chip stack with vertical interconnection" - 54th Electronic Components and Technology Conf Las Vegas, Nevada, May 2004-pp 601-609.
6. M Umemoto et Al - "High-Performance Vertical Interconnection for high density 3D Chip Stacking Package" 54th Electronic Components and Technology Conf, Las Vegas, Nevada, May 2004, pp.616-623.
7. Seong Joon Ok, et Al - "high density, high aspect ratio through-wafer electrical interconnect vias for MEMS packaging", IEEE transactions on advanced packaging, vol 26, No3, august 2003.
8. Chow E.M. et Al - "Though wafer electrical interconnect compatible with standard semiconductor processing", Solid state Sensors and actuators workshop, South Carolina, June 4-8 2000, pp 343-6.
9. Chandrasekaran V. et Al - "Through wafer electrical interconnects for MEMS sensors", ASME International mechanical Engineering Congress and exposition November 11-16 2001.
10. P.S. Andry et Al - "A CMOS compatible process for fabricating electrical through vias in Silicon", ECTC 2006, San Diego 30-05 / 02-06 2006.
11. N. Lietaer, et Al - "Development of cost effective high density through wafer interconnect for 3D microsystems", Journal of micromechanics and microengineering, 2006, Vol 16, S29-S34.
12. U. Heinle, et Al - "Vertical high voltage devices on thick SOI with back-end trench formation", ESSDERC 2002.
13. Yong Zhu, et Al - "Fabrication of Keyhole free ultra-deep high aspect ratio isolation trench and its applications", Journal of micromechanics and microengineering, 2005, Vol 15, 636-642
14. th ECTC 29/05 - 01-06 2007, Reno.