Design and development of a multi-die embedded micro wafer level package

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2008, Pages 1544-1549

  Kripesh, Vaidyanathan ^a   Rao, Vempati Srinivas ^a   Kumar, Aditya ^a   Sharma, Gaurav ^a   Khong, Chee Houe ^a   Zhang, Xiaowu ^a   Khoo, Yee Mong ^a   Khan, Navas ^a   Lau, John ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ARSENIC COMPOUNDS; AUTOMOBILE ELECTRONIC EQUIPMENT; CHIP SCALE PACKAGES; COMPUTER NETWORKS; DIES; ELECTRIC CONNECTORS; ELECTRONICS INDUSTRY; FLIP CHIP DEVICES; INTEGRATION; LAPTOP COMPUTERS; MINIATURE INSTRUMENTS; PACKAGING; PACKAGING MATERIALS; PERSONAL COMPUTERS; PRINTED CIRCUIT BOARDS; PRINTED CIRCUIT MANUFACTURE; PRINTED CIRCUITS; SEMICONDUCTING SILICON COMPOUNDS; SILICON; SILICON WAFERS; STRUCTURAL ANALYSIS; TELECOMMUNICATION EQUIPMENT; WAFER BONDING; WIRE;

ELECTRONIC COMPONENTS; WAFER-LEVEL PACKAGING; WIRE BONDING;

ELECTRONICS PACKAGING;

EID: 51349144172     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2008.4550181     Document Type: Conference Paper

References (19)

1. see http://public.itrs.net
2. J.-C. Souriau et al., "Wafer Level Processing of 3D System in Package for RF and Data Applications", 55th Electronic Components and Technology Conf, Lake Buena Vista, FL, June 2005, p. 356
3. S.N. Towle et al. "Bumpless Built-Up Layer Packaging", ASME International Mechanical Engineering Congress and Exposition, New York, NY, Nov. 2001
4. D. Komatsu and T. Wakabayashi, "Trend of WLP Technology and Next Generation Packaging "WLP and EWLP", 5th International Workshop on Microelectronics Assembly and Packaging & Reverse Trade Show, Fukuoka, Japan, 15-16. Sept. 2005
5. P. Maruscheck, J. Evers, W. Schaefer, M. Nienhaus, and S. Kleen, "A field mill based on the modular MEMS framework MATCH-X," in Proc. Actuator 2002, Bremen, Germany, June 10-12, 2002, pp. 316-320.
6. M. Klein, H. Oppermann, R. Aschenbrenner, and H. Reichl, "Modular systems for sensor integration," in Proc. IMAPS 2002, Denver, CO, pp. 194-198.
7. V. Solberg, "Innovative 3D solutions for multiple die packaging," in Proc. SMTA 2003, IL, pp. 626-630.
8. T. Hamano et al., "Super CSPTM : WLCSP Solution for Memory and System LSI", in proceedings of International Symposium on Advanced Packaging Materials 1999.
9. A. Okuno, "Wafer Level CSP Process by VPES(Vacuum Printing Encapsulation Systems)", in proceedings of International Symposium on Electronics Materials & Packaging 2000.
10. T. Braun et al., "Wafer Level Encapsulation - A transfer Molding Approach to System in Package Generation", in proceedings of EPTC 2002, Singapore.
11. R. Aschenbrenner et al., "Process Flow and Manufacturing Concept for Embedded Active Devices", in proceedings of EPTC 2004, Singapore.
12. C. T. Ko et al, "Embedded Active Device Packaging Technoloogy for Next-Generation Chip-in-Substrate Packages, CiSP", in proceedings of ECTC 2006, US.
13. J. C. Souriau et al, "Wafer Level Processing on Re-built Wafer for Chip Staking", in proceedings EPTC 2005, Singapore.
14. M. Brunnbauer et al., "An Embedded Device Technology Based on a Molded Reconfigured Wafer", in proceedings of ECTC 2006, US.
15. B. Keser et al., "The Redistributed Chip Package: A Breakthrough for Advanced Packaging", in proceedings of ECTC 2007
16. Ahmer Syed, "Accumulated Creep Strain and Energy Density Based Thermal Fatigue Life Prediction Models for SnAgCu Solder Joints", in proceedings of ECTC 2004.
17. M. G. Pecht, et al, "Electronic Packaging Materials and Their Properties", CRC Press LLC, Boca Raton, 1998.
18. Lau, J. H., and W. Dauksher, "Creep of Sn-(3.5-3.9)wt%Ag-(0.5-0.8) wt%Cu Lead-Free Solder", in Micromaterials and Nanomaterials, Edited by B. Michel, Fraunhofer Institute, IZM, Berlin, 2004, pp. 54-62.
19. Yuan Li, "Accurate Predictions of Flip Chip BGA Warpage", in proceedings of ECTC 2003.