Super CSPTM: WLCSP solution for memory and system LSI

Proceedings - International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces

Volumn , Issue , 1999, Pages 221-225

  Hamano, T ^a   Kawahara, T ^a   Kasai, J I ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DIES; ELECTRONICS PACKAGING; INTERFACES (MATERIALS); PACKAGING MATERIALS; SOLDERING;

CHIP SIZE PACKAGE; ELECTRICAL PERFORMANCE; PACKAGE RELIABILITY; PACKAGING RELIABILITIES; SYSTEM DESIGNERS; WAFER LEVEL CSP; WAFER LEVEL PACKAGING; WAFER LEVEL TESTING;

PACKAGING;

EID: 51349130607     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISAPM.1999.757316     Document Type: Conference Paper

References (4)

1. J. Kasai, "Overview of Wafer Level CSP Achieving both Chip Size and Low Cost" (in Japanese), The 17th Nikkei Microdevice Packaging Seminar, June 1998
2. H. Matsuki, Y. Shinma, K. Nagashige, Y. Hamanaka, N. Fukasawa, M. Morioka, M. Onodera, T. Uno, and T. Kawahara, "Super CSP: A BGA Type Real Chip Size Package using a New Encapsulation Method", The 1998 Proceedings of Pan Pacific Microelectronics Symposium, February 1998, pp415-419
3. M. Hou, "Super CSP: The Wafer Level Package", The Proceedings of Semiconductor Packaging Symposium, Session V: Chipscale Packaging, SEMICON® West 98, July 1998, pp. F-l-F-10
4. Y. Yoneda, "Super CSPTM", The Proceedings of SEMI Technology Symposium 98, SEMICON Japan 98, December 1998, pp. 8-93-8-98