-
2
-
-
33645798888
-
Analysis and architecture design of variable block-size motion, estimationfor H.264/AVC
-
Mar.
-
C.-Y. Chen, S.-Y. Chien, Y.-W. Huang, T.-C. Chen, T.-C. Wang, and L.-G. Chen, "Analysis and architecture design of variable block-size motion, estimationfor H.264/AVC," IEEE Trans. Circuits Syst. I: RegularPapers, vol.53, no.3, pp. 578-593, Mar. 2006.
-
(2006)
IEEE Trans. Circuits Syst. I: RegularPapers
, vol.53
, Issue.3
-
-
Chen, C.-Y.1
Chien, S.-Y.2
Huang, Y.-W.3
Chen, T.-C.4
Wang, T.-C.5
Chen, L.-G.6
-
3
-
-
0034250641
-
Low-power VLSI design for motion estimation using adaptive pixel truncation
-
Aug.
-
Z.-L. He, C.-Y. Tsui, K.-K. Chan, and M. L. Liou, "Low-power VLSI design for motion estimation using adaptive pixel truncation," IEEE Trans. Cirvuits Syst. Video Technol, vol.10, no.5, pp. 669-678, Aug. 2000.
-
(2000)
IEEE Trans. Cirvuits Syst. Video Technol
, vol.10
, Issue.5
-
-
He, Z.-L.1
Tsui, C.-Y.2
Chan, K.-K.3
Liou, M.L.4
-
5
-
-
47649090257
-
Low-power hardware architecture for vbsme using pixel truncation
-
Hyderabad, Andhra Pradesh
-
A. Bahari, T. Arslan, and A. Erdogan, "Low-power hardware architecture for vbsme using pixel truncation," in Proc. 21st Int. Conf. VLSI Design, Hyderabad, Andhra Pradesh, 2008, pp. 389-394.
-
(2008)
Proc. 21st Int. Conf. VLSI Design
-
-
Bahari, A.1
Arslan, T.2
Erdogan, A.3
-
6
-
-
0031210894
-
Low-complexity block-based motion estimation via one-bit transforms
-
Aug.
-
B. Natarajan, V. Bhaskaran, and K. Konstantinides, "Low-complexity block-based motion estimation via one-bit transforms," IEEE Trans. Circuits Syst. Video Technol, vol.7, no.4, pp. 702-706, Aug. 1997.
-
(1997)
IEEE Trans. Circuits Syst. Video Technol
, vol.7
, Issue.4
-
-
Natarajan, B.1
Bhaskaran, V.2
Konstantinides, K.3
-
7
-
-
23744490030
-
Two-bit transform for binary block motion estimation
-
Jul.
-
A. Erturk and S. Erturk, "Two-bit transform for binary block motion estimation," IEEE Trans. Circuits Syst. Video Technol, vol.15, no.7, pp. 938-946, Jul. 2005.
-
(2005)
IEEE Trans. Circuits Syst. Video Technol
, vol.15
, Issue.7
-
-
Erturk, A.1
Erturk, S.2
-
8
-
-
0032183261
-
New motion estimation algorithm, using adaptively quantized low bit-resolut.ionim.age and its VLSI architecture for MP.EG2 video encoding
-
Oct.
-
S. Lee, J.-M. Kim, and S.-I. Chae, "New motion estimation algorithm, using adaptively quantized low bit-resolut.ionim.age and its VLSI architecture for MP.EG2 video encoding," IEEE Trans. Circuits Syst. Video Technol, vol.8, no.6, pp. 734-744, Oct. 1998.
-
(1998)
IEEE Trans. Circuits Syst. Video Technol
, vol.8
, Issue.6
-
-
Lee, S.1
Kim, J.-M.2
Chae, S.-I.3
-
9
-
-
0029489883
-
Multi-level pixel difference classification methods
-
Washington D.C
-
Y. Chan and S. Kung, "Multi-level pixel difference classification methods," in Proc. IEEE Int. Conf. Image Pr-ocess., vol.3. Washington D.C, 1995, pp. 252-255.
-
(1995)
Proc. IEEE Int. Conf. Image Process.
, vol.3
-
-
Chan, Y.1
Kung, S.2
-
10
-
-
0032632545
-
Msb truncation scheme for low-power video processors
-
Orlando, FL
-
V. G. Moshnyaga, "Msb truncation scheme for low-power video processors," in Proc. IEEE Int. Symp. Circuits Syst., vol.4. Orlando, FL, 1999, pp. 291-294.
-
(1999)
Proc. IEEE Int. Symp. Circuits Syst.
, vol.4
-
-
Moshnyaga, V.G.1
-
11
-
-
0029325213
-
A new blockmatching criterion for motion estimation and its implementation
-
Jun.
-
M.-J. Chen, L.-G. Chen, T.-D. Chiueh, and Y.-P. Lee, "A new blockmatching criterion for motion estimation and its implementation," IEEE Trans. Circuits Syst. Video Technol, vol.5, no.3, pp. 231-236, Jun. 1995.
-
(1995)
IEEE Trans. Circuits Syst. Video Technol
, vol.5
, Issue.3
-
-
Chen, M.-J.1
Chen, L.-G.2
Chiueh, T.-D.3
Lee, Y.-P.4
-
12
-
-
28244442508
-
Pre-decision strategy for coded/non-coded MBs in MPEG4
-
Bangalore, India
-
S. Sharma, P. Mishra, S. Sawant, C. P. Mammen, and V. M. Gadre, "Pre-decision strategy for coded/non-coded MBs in MPEG4," in Proc. Int. Conf. Signal Process. Commun. 2004 (SPCOM), Bangalore, India, 2004, pp. 501-505.
-
(2004)
Proc. Int. Conf. Signal Process. Commun. 2004 (SPCOM)
-
-
Sharma, S.1
Mishra, P.2
Sawant, S.3
Mammen, C.P.4
Gadre, V.M.5
-
13
-
-
0030378719
-
A novel architecture and processor-level design, based on a new matching criterion, for video compression
-
San Francisco, CA
-
H. Yeo and Y. H. Hu, "A novel architecture and processor-level design, based on a new matching criterion, for video compression," in Proc. Workshop VLSI Signal Process., IX, San Francisco, CA, 1996, pp. 448-457.
-
(1996)
Proc. Workshop VLSI Signal Process., IX
-
-
Yeo, H.1
Hu, Y.H.2
-
14
-
-
34247556136
-
Fast algorithm, and architecture design of low-power integer motion estimationfor H.264/AVC
-
May
-
T.-C. Chen, Y.-H. Chen, S.-F. Tsai, S. Y. Chien, and L. G. Chen, "Fast algorithm, and architecture design of low-power integer motion estimationfor H.264/AVC," IEEE Trans. Circuits Syst. Video Technol, vol.17, no.5, pp. 568-577, May 2007.
-
(2007)
IEEE Trans. Circuits Syst. Video Technol
, vol.17
, Issue.5
-
-
Chen, T.-C.1
Chen, Y.-H.2
Tsai, S.-F.3
Chien, S.Y.4
Chen, L.G.5
-
15
-
-
4444267593
-
A sub-mw MPEG-4 motion estimation processor core for mobile video application
-
Sep.
-
M. Miyama, J. Miyakoshi, Y. Kuroda, K. Imamura, H. Hashimoto, and M. Yoshimoto, "A sub-mw MPEG-4 motion estimation processor core for mobile video application," IEEE J. Solid-State Circuits, vol.39, no.9, pp. 1562-1570, Sep. 2004.
-
(2004)
IEEE J. Solid-State Circuits
, vol.39
, Issue.9
-
-
Miyama, M.1
Miyakoshi, J.2
Kuroda, Y.3
Imamura, K.4
Hashimoto, H.5
Yoshimoto, M.6
-
16
-
-
0037745733
-
Parallel 4*4 2d transform, and inverse transform, architecture for MPEG-4 H.264/AVC
-
T.-C. Wang, Y.-W. Huang, H.-C. Fang, and L.-G. Chen, "Parallel 4*4 2d transform, and inverse transform, architecture for MPEG-4 H.264/AVC," in Proc, IEEE Int. Symp. Circuits Syst. 2003, vol.2. pp. 800-803.
-
(2003)
Proc, IEEE Int. Symp. Circuits Syst.
, vol.2
-
-
Wang, T.-C.1
Huang, Y.-W.2
Fang, H.-C.3
Chen, L.-G.4
-
17
-
-
84908483284
-
Architecture design for deblocking filter in H.264/jvt/AVC
-
Y.-W. Huang, T.-W. Chen, B.-Y. Hsieh, T.-C. Wang, T.-H. Chang, and L.G. Chen, "Architecture design for deblocking filter in H.264/jvt/AVC," in Proc. Int. Conf. Multimedia Expo 2003, vol.1. pp. 693-696.
-
(2003)
Proc. Int. Conf. Multimedia Expo
, vol.1
-
-
Huang, Y.-W.1
Chen, T.-W.2
Hsieh, B.-Y.3
Wang, T.-C.4
Chang, T.-H.5
Chen, L.G.6
-
18
-
-
18844395041
-
A platform based bus-interleaved architecture for de-blocking filter in MPEG-4 H.264/AVC
-
Feb.
-
S.-C. Chang, W.-H. Peng, S.-H. Wang, and T. Chiang, "A platform based bus-interleaved architecture for de-blocking filter in MPEG-4 H.264/AVC," IEEE Trans. Consumer Electron., vol.51, no.1, pp. 249-255, Feb. 2005.
-
(2005)
IEEE Trans. Consumer Electron.
, vol.51
, Issue.1
-
-
Chang, S.-C.1
Peng, W.-H.2
Wang, S.-H.3
Chiang, T.4
-
19
-
-
33745434453
-
Dual-block-pipelined VLSI architecture of entropy coding for H.264/AVC baseline profile
-
Hsinchu, Taiwan
-
T.-C. Chen, Y.-W. Huang, C.-Y. Tsai, B.-Y. Hsieh, and L.-G. Chen, "Dual-block-pipelined VLSI architecture of entropy coding for H.264/AVC baseline profile," in Proc. IEEE VLSI-TSA Int. Symp. VLSI Design, Automation Test, 2005 (VLSI-TSA-DAT), Hsinchu, Taiwan, pp. 271-274.
-
Proc. IEEE VLSI-TSA Int. Symp. VLSI Design, Automation Test, 2005 (VLSI-TSA-DAT)
-
-
Chen, T.-C.1
Huang, Y.-W.2
Tsai, C.-Y.3
Hsieh, B.-Y.4
Chen, L.-G.5
-
20
-
-
33746358201
-
Analysis and architecture design of an hdtv720p 30 frames/s H.264/AVC encoder
-
Jun.
-
T.-C. Chen, S.-Y. Chien, Y.-W. Huang, C.-H. Tsai, C.-Y. Chen, T.-W. Chen, and L.-G. Chen, "Analysis and architecture design of an hdtv720p 30 frames/s H.264/AVC encoder," IEEE Trans. Circuits Syst. Video Technol, vol.16, no.6, pp. 673-688, Jun. 2006.
-
(2006)
IEEE Trans. Circuits Syst. Video Technol
, vol.16
, Issue.6
-
-
Chen, T.-C.1
Chien, S.-Y.2
Huang, Y.-W.3
Tsai, C.-H.4
Chen, C.-Y.5
Chen, T.-W.6
Chen, L.-G.7
|