A 32Gb/s on-chip bus with driver pre-emphasis signaling

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2006, Pages 265-268

  Zhang, Liang ^a   Wilson, John ^a   Bashirullah, Rizwan ^b   Luo, Lei ^a   Xu, Jian ^a   Franzon, Paul ^a  

^a North Carolina State University   (United States)

^b UNIVERSITY OF FLORIDA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY LATENCY; LOSSY INTERCONNECTS;

CHIP SCALE PACKAGES; CMOS INTEGRATED CIRCUITS; CROSSTALK; INTERCONNECTION NETWORKS;

BUSBARS;

EID: 39049121265     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2006.320855     Document Type: Conference Paper

References (13)

1. C. Hu, "CMOS for one more century?" Custom Integrated Circuits Conference, Keynote Speech, Oct 2004.
2. R. Ho, K. W. Mai, and M. A. Horowitz, "The future of wires," Proc. IEEE, vol. 89, no. 4, pp. 490-504, Apr 2001.
3. H. Bakoglu, Circuits, Interconnections and Packaging for VLSI, Addison-Wesley, 1990.
4. J. Cong, "An interconnect-centric design flow for nanometer technologies," Proc. of the IEEE, vol. 89, no. 4, pp. 505-528, Apr 2001.
5. R. Bashirullah, et.al., "A 16Gb/s adaptive banwidth on-chip bus based on hybrid current/voltage mode signaling," Symp. VLSI Circuits, pp. 392-393, June 2004.
6. N. Tzartzanis and W. W. Walker, "Differential current-mode sensing for efficient on-chip global signaling," JSSC, vol. 40, pp. 2141-2147, Nov 2005.
7. W. Dally and J. Poulton, Digital Systems Engineering, Cambridge Univ. Press, Cambridge, UK, 1997.
8. B. Nikolic, et al., "Improved sense-amplifier-based flip-flog design and measurements," JSSC, vol. 35, pp. 876-884, Jun 2000.
9. R. Ho, K, Mai, and M. Horowitz, "Efficient on-chip global interconnects," Symp. VLSI Circuits, pp. 271-274, Jun 2003.
10. Y. Ismail, E. Friedman, and J. Neves, "Figures of merit to characterize the importance of on-chip inductance," IEEE Trans. VLSI, vol. 7, pp. 442-449, Dec 1999.
11. K. Banerjee and A. Mehrotra, "A power-optimal repeater insertion methodology for global interconnects in nanometer designs," IEEE Trans. Electron Devices, vol. 49, no. 11, pp. 2001-2007, Nov 2002.
12. D. Burger and T. M. Austin, "The SimpleScalar tool set, version 2.0," University of Wisconsin, Madison, Technical Report CS-TR-97-1342, June 1997.
13. J. M. Rabaey, Degital Integrated Circuits: A Design Perspective, Prentice Hall, 1996.