Exploring speculative parallelism in SPEC2006

ISPASS 2009 - International Symposium on Performance Analysis of Systems and Software

Volumn , Issue , 2009, Pages 77-88

  Packirisamy, Venkatesan ^a   Zhai, Antonia ^a   Hsu, Wei Chung ^a   Yew, Pen Chung ^a   Ngai, Tin Fook ^b  

^a UNIVERSITY OF MINNESOTA   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK RATE; COMPLEX CONTROL FLOW; COMPUTER INDUSTRY; CONTINUOUS IMPROVEMENTS; EXECUTION MODEL; FOUR-CORE; MULTICORE ARCHITECTURES; MULTIPLE LOOPS; MULTITHREADED; PARALLELIZATIONS; PARALLELIZING COMPILER; PERFORMANCE POTENTIALS; PROGRAM PERFORMANCE; SINGLE LOOP; THREAD LEVEL SPECULATION; TRANSACTIONAL MEMORY;

COMPUTER SOFTWARE; SEEBECK EFFECT; SOFTWARE ARCHITECTURE; SURVEYING INSTRUMENTS;

PROGRAM COMPILERS;

EID: 70349176695     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPASS.2009.4919640     Document Type: Conference Paper

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