Tasking with out-of-order spawn in TLS chip multiprocessors: Microarchitecture and compilation

Proceedings of the International Conference on Supercomputing

Volumn , Issue , 2005, Pages 179-188

  Renau, Jose ^a   Tuck, James ^b   Liu, Wei ^b   Ceze, Luis ^b   Strauss, Karin ^b   Torrellas, Josep ^b  

^a University of California Santa Cruz   (United States)

^b University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP MULTIPROCESSORS (CMPS); OUT-OF-ORDER SPAWN; TASK ORDERING; THREAD-LEVEL SPECULATION (TLS);

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; PROGRAM COMPILERS; RESOURCE ALLOCATION;

MICROPROCESSOR CHIPS;

EID: 32844465384     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1088149.1088173     Document Type: Conference Paper

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