Technology development & design for 22 nm InGaAs/InP-channel MOSFETs

Conference Proceedings - International Conference on Indium Phosphide and Related Materials

Volumn , Issue , 2008, Pages

  Rodwell, M J W ^a   Wistey, M ^a   Singisetti, U ^a   Burek, G ^a   Gossard, A ^a   Stemmer, S ^a   Engel Herbert, R ^a   Hwang, Y ^a   Zheng, Y ^a   Van De Walle, C ^a   Asbeck, P ^b   Taur, Y ^b   Kummel, A ^b   Yu, B ^b   Wang, D ^b   Yuan, Y ^b   Palmstrom C ^c   Arkun, Erdem ^c   Simmonds, Paul ^c   McIntyre, P ^d   Harris, J ^d   Fischetti, M V ^e   Sachs, C ^e   more..

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c UNIVERSITY OF MINNESOTA   (United States)

^d STANFORD UNIVERSITY   (United States)

^e UNIVERSITY OF MASSACHUSETTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CARRIER VELOCITY; CHANNEL LAYERS; DESIGN CHALLENGES; DEVICE DESIGN; DRIVE CURRENTS; ELECTRICAL PARAMETER; ELECTRON EFFECTIVE MASS; ENHANCEMENT-MODE; FULLY SELF-ALIGNED; GATE METALS; GROWTH PROCESS; INGAAS/INP; LOW DENSITY; MOSFETS; POTENTIAL APPLICATIONS; SELF-ALIGNED; SOURCE AND DRAINS; TECHNOLOGY DEVELOPMENT;

GATE DIELECTRICS; GATES (TRANSISTOR); INDIUM; INDIUM PHOSPHIDE; MOSFET DEVICES; TECHNOLOGICAL FORECASTING; VLSI CIRCUITS;

DIELECTRIC MATERIALS;

EID: 70149105093     PISSN: 10928669     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICIPRM.2008.4703065     Document Type: Conference Paper

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