A 32-Gb/s on-chip bus with driver pre-emphasis signaling

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 17, Issue 9, 2009, Pages 1267-1274

  Zhang, Liang ^a   Wilson, John M ^b,c   Bashirullah, Rizwan ^d   Luo, Lei ^b   Xu, Jian ^e   Franzon, Paul D ^c  

^a IDT Atlanta Design Center   (United States)

^b North Carolina State University   (United States)

^c RAMBUS INC   (United States)

^d University of Florida   (United States)

^e ARM   (United States)

Author keywords

Interconnects; Low power; On chip; Pre emphasis

Indexed keywords

BUS ARCHITECTURE; BUS DESIGN; CROSSTALK NOISE; DATA RATES; DIFFERENTIAL CURRENT; INTERCONNECTS; LOW POWER; ON-CHIP; ON-CHIP BUS; ON-CHIP GLOBAL INTERCONNECTS; PEAK CURRENTS; POWER DISSIPATION; POWER REDUCTIONS; PRE-EMPHASIS; ROUTING AREA; SIGNAL ACTIVITY; SIGNAL DELAYS; SINGLE-ENDED; VOLTAGE MODE;

ACTIVE FILTERS; ARCHITECTURAL DESIGN; ELECTRIC POTENTIAL; ELECTRIC POWER UTILIZATION;

SIGNALING;

EID: 69649090283     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2002682     Document Type: Article

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