Investigation on maximal throughput of a CMOS repeater chain

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 47, Issue 4, 2000, Pages 602-606

  Larsson Edefors, Per ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; DATA TRANSFER; ELECTRIC INVERTERS; ELECTRIC POWER SUPPLIES TO APPARATUS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS;

CASCADED INVERTER; OFF-CHIP DATA SIGNALS; REPEATER CHAIN;

CMOS INTEGRATED CIRCUITS;

EID: 0033741257     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/81.841866     Document Type: Article

References (7)

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