On the scaling of flash cell spacer for gate disturb and charge retention optimization

IEEE Transactions on Electron Devices

Volumn 56, Issue 9, 2009, Pages 1959-1965

  Lee, Yung Huei ^a   McMahon, William ^a   Lu, Yin Lung Ryan ^b   Tewg, Jun Yen J ^b   Ma, Sean T ^b  

^a RandD   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Cell scaling; Charge retention; Gate disturb; Selfaligned contact (SAC) architecture; Spacer oxide

Indexed keywords

AGGRESSIVE SCALING; CHARGE RETENTION; CONTACT PROCESS; FLASH CELL; FLOATING GATES; GATE DISTURB; HIGH QUALITY; INDUCED CHARGES; NOR FLASH; SELF-ALIGNED; SELFALIGNED CONTACT (SAC) ARCHITECTURE; SHIFT-AND; SIDEWALL SPACER; SPACER OXIDE;

ARCHITECTURAL DESIGN; CELL MEMBRANES;

GATE DIELECTRICS;

EID: 69549137962     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2025912     Document Type: Article

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