A self-aligned contact architecture with W-gate for NOR flash technology scaling

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 2007, Pages

  Blosse, A ^a   Wei, M ^a   Bhachawat, V ^a   Hineman, M ^a   Koval, R ^a   Gorman, J ^a   Kau, D ^a   Tewg, J ^a   Wang, L ^a   Hajra, M ^a   Schroeder, P ^a   Woo, B J ^a   Fazio, A ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL INTEGRATED CIRCUITS; FLASH MEMORY; SEMICONDUCTOR DEVICE MANUFACTURE;

CELL HEIGHT SCALING; FUNCTIONAL TEST STRUCTURES;

GATES (TRANSISTOR);

EID: 34548846160     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2007.378934     Document Type: Conference Paper

References (3)

1. G. Servalli, D. Brazzelli, et al., IEEE IEDM Tech. Dig., 2005, pp. 849-852.
2. B. Jin, Y. Kim, et al., Symposium on VLSI Tech. Dig., 2001, pp. 127-128.
3. A. Blosse, K. Ramkumar, et.al., IEEE IEDM Tech. Dig. 2004, pp. 669-672.