A 45nm NOR flash technology with Self-Aligned Contacts and 0.024μm 2 cell size for multi-level applications

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 2008, Pages 81-82

  Fastow, R ^a   Banerjee, R ^a   Bjeletich, P ^a   Brand, A ^a   Chao, H ^a   Gorman, J ^a   Guo, X ^a   Heng, J B ^a   Koenigsfeld, N ^a   Ma, S ^a   Masad, A ^a   Soss, S ^a   Woo, B J ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; SECURITY SYSTEMS;

DIE AREA; INTERNATIONAL SYMPOSIUM; NOR FLASH; SELF ALIGNING; SELF-ALIGNED; VLSI TECHNOLOGIES;

TECHNOLOGY;

EID: 49049086067     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2008.4530808     Document Type: Conference Paper

References (3)

1. J. Kim, et al, IEDM Technical Digest, pp. 979-982, 1998.
2. A. Blosse, et al., VLSI-TSA Technical Digest, pp.1-2, April 2007.
3. M.Wei, et al., in VLSI Technology Symposium Japan, 2007