Design, implementation and on-chip high-speed test of sfq half-precision floating-point multiplier

IEEE Transactions on Applied Superconductivity

Volumn 19, Issue 3, 2009, Pages 657-660

  Hara, Hiroshi ^a   Obata, Koji ^b   Park, Heejoung ^a   Yamanashi, Yuki ^a   Taketomi, Kazuhiro ^a   Yoshikawa, Nobuyuki ^a   Tanaka, Masamitsu ^b   Fujimaki, Akira ^b   Takagi, N ^b   Takagi, Kazuyoshi ^b   Nagasawa, S ^a  

^a YOKOHAMA NATIONAL UNIVERSITY   (Japan)

^b NAGOYA UNIVERSITY   (Japan)

Author keywords

Floating point units; LSRDP; Multiplier; SFQ circuits; Superconducting integrated circuits

Indexed keywords

FLOATING POINT UNITS; LSRDP; MULTIPLIER; SFQ CIRCUITS; SUPERCONDUCTING INTEGRATED CIRCUITS;

DIGITAL INTEGRATED CIRCUITS; FREQUENCY MULTIPLYING CIRCUITS; INTEGRATED CIRCUITS; NIOBIUM; PASSIVE NETWORKS; SUPERCONDUCTIVITY;

SQUIDS;

EID: 68649115719     PISSN: 10518223     EISSN: None     Source Type: Journal    
DOI: 10.1109/TASC.2009.2018039     Document Type: Conference Paper

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