Top-down RSFQ logic design based on a binary decision diagram

IEEE Transactions on Applied Superconductivity

Volumn 11, Issue 1 I, 2001, Pages 1098-1101

  Yoshikawa, N ^a   Koshiyama, J ^a  

^a YOKOHAMA NATIONAL UNIVERSITY   (Japan)

Author keywords

Binary decision diagram; CAD; Design technology; RSFQ; Superconducting electronics

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; DECISION TABLES; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; LOGIC DESIGN; LOGIC GATES; TRANSISTORS;

BINARY DECISION DIAGRAM; LOGIC CELL LIBRARY; RAPID SINGLE FLUX QUANTUM INTEGRATED CIRCUITS; SUPERCONDUCTING ELECTRONICS;

SUPERCONDUCTING DEVICES;

EID: 0035268109     PISSN: 10518223     EISSN: None     Source Type: Journal    
DOI: 10.1109/77.919539     Document Type: Conference Paper

References (10)

1. RSFQ logic/memory family: A new Josephson-junction technology for sub-terahertz-clock frequency digital systems
2. Implementation of oversampling analog-to-digital converter based on RSFQ logic
3. Tools for the computer-aided design of multigigahertz superconducting digital circuits
4. A new design approach for RSFQ logic circuits based on the binary decision diagram
5. A cell-based design approach for RSFQ circuits using binary decision diagram
6. Binary decision diagram
7. Overview of low-power ULSI circuit techniques
8. Data-driven self-timed RSFQ demultiplexer
9. Functional modeling of RSFQ circuits using verilog HDL
10. A Josephson integrated circuit simulator (JSIM) for superconductive electronics application