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Volumn 12, Issue 11, 1999, Pages 782-785

Cell-based design approach for RSFQ circuits using a binary decision diagram

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; FLIP FLOP CIRCUITS; JOSEPHSON JUNCTION DEVICES; LOGIC GATES; TRANSMISSION LINE THEORY;

EID: 0033226118     PISSN: 09532048     EISSN: None     Source Type: Journal    
DOI: 10.1088/0953-2048/12/11/327     Document Type: Article
Times cited : (9)

References (9)
  • 1
    • 0026116572 scopus 로고
    • RSFQ logic/memory family: A new Josephson-junction technology for sub-terahertz-clock frequency digital systems
    • Likharev K K and Semenov V K 1991 RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock frequency digital systems IEEE Trans. Appl. Supercond. 1 1-28
    • (1991) IEEE Trans. Appl. Supercond. , vol.1 , pp. 1-28
    • Likharev, K.K.1    Semenov, V.K.2
  • 2
    • 0032639093 scopus 로고    scopus 로고
    • A new approach for RSFQ logic circuits based on the binary decision diagram
    • Yoshikawa N, Tago H and Yoneyama K 1999 A new approach for RSFQ logic circuits based on the binary decision diagram IEEE Trans. Appl. Supercond. 9 3161-4
    • (1999) IEEE Trans. Appl. Supercond. , vol.9 , pp. 3161-3164
    • Yoshikawa, N.1    Tago, H.2    Yoneyama, K.3
  • 3
    • 0017983865 scopus 로고
    • Binary decision diagrams
    • Akers S B 1978 Binary decision diagrams IEEE Trans. Comput. 27 509-16
    • (1978) IEEE Trans. Comput. , vol.27 , pp. 509-516
    • Akers, S.B.1
  • 4
    • 0022769976 scopus 로고
    • Graph-based algorithms for Boolean function manipulation
    • Bryant R E 1986 Graph-based algorithms for Boolean function manipulation IEEE Trans. Comput. 35 677-91
    • (1986) IEEE Trans. Comput. , vol.35 , pp. 677-691
    • Bryant, R.E.1
  • 8
    • 0026123167 scopus 로고
    • A multi-gigahertz Josephson flash A/D converter with a pipelined encoder using large-dynamic-range current-latch comparators
    • Fang E S, Hebert D and Van Duzer T 1991 A multi-gigahertz Josephson flash A/D converter with a pipelined encoder using large-dynamic-range current-latch comparators IEEE Trans. Magn. 27 2891-4
    • (1991) IEEE Trans. Magn. , vol.27 , pp. 2891-2894
    • Fang, E.S.1    Hebert, D.2    Van Duzer, T.3
  • 9
    • 0032167314 scopus 로고    scopus 로고
    • Monte Carlo optimization of superconducting complementary output switching logic circuits
    • Jeffry M, Perold W, Wang W and Van Duzer T 1998 Monte Carlo optimization of superconducting complementary output switching logic circuits IEEE Trans. Appl. Supercond. 8 104-19
    • (1998) IEEE Trans. Appl. Supercond. , vol.8 , pp. 104-119
    • Jeffry, M.1    Perold, W.2    Wang, W.3    Van Duzer, T.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.