High-end server based on complexity-reduced architecture for superconductor technology

IEICE Transactions on Electronics

Volumn E85-C, Issue 3, 2002, Pages 612-616

  Fujimaki, Akira ^a   Takai, Yoshiaki ^b   Yoshikawa, Nobuyuki ^c  

^a NAGOYA UNIVERSITY   (Japan)

^b HOKKAIDO UNIVERSITY   (Japan)

^c YOKOHAMA NATIONAL UNIVERSITY   (Japan)

Author keywords

JAVA; Memory; Processor; SFQ; Superconducting circuit

Indexed keywords

BANDWIDTH; COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER ARCHITECTURE; JAVA PROGRAMMING LANGUAGE; LOGIC CIRCUITS; SUPERCONDUCTING DEVICES;

COMPLEXITY-REDUCED ARCHITECTURE; JAVA BYTE CODES; SINGLE FLUX QUANTUM CIRCUIT; SUPERCONDUCTING CIRCUIT;

SERVERS;

EID: 0036505091     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (16)

1. RSFQ logic/memory family: A new Josephson-junction technology for sub-terahertz-clock frequency digital systems
2. Superconductor electronic devices for petaflops computing
3. VLSIs in the year 2010 and beyond
4. Roadmap of superconducting digital electronics toward 2001
5. Report on roadmap for superconducting electronics
6. High performance Nb Josephson devices for petaflop computing
7. y/Nb structure for integrated circuit application
8. y/Nb junctions based on the proximity effect
9. A new concept for ultra-low power and ultra-high power clock rate circuits
10. Demonstration of chip-to-chip propagation of single flux quantum pulses
11. Josephson-CMOS memories
12. On-chip test of the shift-register for high-end network switch based on cell-based design
13. Josephson-CMOS memories
14. Cell-based top-down design methodology for RSFQ digital circuits
15. Can low-cost, high-reliability cryocoolers be are reality?