74 dB SNDR multi-loop sturdy-mash delta-sigma modulator using 35 db open-loop opamp gain

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 8, 2009, Pages 2212-2221

  Maghari, Nima ^a   Kwon, Sunwoo ^a   Moon, Un Ku ^a  

^a Oregon State University   (United States)

Author keywords

Analog to digital conversion; CMOS analog integrated circuits; Delta sigma modulation; Switched capacitor circuits

Indexed keywords

ANALOG-TO-DIGITAL CONVERSION; CMOS ANALOG INTEGRATED CIRCUITS; CMOS TECHNOLOGY; DELTA SIGMA MODULATOR; FOURTH ORDER; HIGH DC GAIN; LOOP STRUCTURE; LOW VOLTAGE OPERATION; MEASUREMENT RESULTS; NOISE TRANSFER FUNCTION; OPEN LOOPS; OVER SAMPLING RATIO; POWER-SUPPLY RAILS; SAMPLING FREQUENCIES; SWITCHED-CAPACITOR CIRCUITS; SYSTEM REQUIREMENTS; TOTAL POWER DISSIPATION;

ANALOG CIRCUITS; CAPACITANCE; CAPACITORS; CMOS INTEGRATED CIRCUITS; DELTA SIGMA MODULATION; DIGITAL FILTERS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ELECTRIC POWER UTILIZATION; INTEGRATED CIRCUITS; LINEAR INTEGRATED CIRCUITS; MOBILE TELECOMMUNICATION SYSTEMS; MODULATION; OPERATIONAL AMPLIFIERS; TIME VARYING SYSTEMS; TRANSIENTS;

MODULATORS;

EID: 68549096221     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2022302     Document Type: Article

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