Mixed-order sturdy MASH Δ-∑ modulator

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 257-260

  Maghari, N ^a   Kwon, S ^a   Ternes, G C ^a   Moon, U ^a  

^a Oregon State University

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC FILTERS; MODULATORS; NOISE ABATEMENT; NUMERICAL METHODS; SENSITIVITY ANALYSIS;

DIGITAL NOISE CANCELLATION FILTERS; IMPERFECT CIRCUIT BLOCKS; MASH STRUCTURE; NOISE SHAPING;

DELTA SIGMA MODULATION;

EID: 34548831070     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters, Piscataway, NJ: IEEE Press 2005.
2. N. Maghari, S. Kwon, G. C. Temes, and U. Moon, "Sturdy MASH Δ-∑ Modulator," Electron. Lett., vol. 42, pp. 1269-1270, Oct. 2006.
3. P. Benabes, A. Gauthier, and R. Kielbasa,"New High-Order Universal ∑Δ Modulators," Electron. Lett., vol. 31, pp. 8-9, Jan. 1995.
4. I. Fujimori et al., "A 90-dB SNR 2.5-MHz Output-Rate ADC Using Cascaded Multibit Delta-Sigma Modulation at 8× Oversampling Ratio," IEEE J. Solid-State Circuits, vol. 35, pp. 1820-1828, Dec. 2000.
5. S. Kwon and F. Maloberti, "A 14mW Multi-bit Delta-Sigma Modulator with 82dB SNR and 86dB DR for ADSL2+," in ISSCC Dig. Tech. Papers, Feb. 2006, pp. 68-69.