-
1
-
-
0000195442
-
"Computer-aided design of analog and mixed-signal integrated circuits"
-
Dec
-
G. Gielen and R. A. Rutenbar, "Computer-aided design of analog and mixed-signal integrated circuits," Proc. IEEE, vol. 88, no. 12, pp. 1825-1854, Dec. 2000.
-
(2000)
Proc. IEEE
, vol.88
, Issue.12
, pp. 1825-1854
-
-
Gielen, G.1
Rutenbar, R.A.2
-
2
-
-
0036612580
-
"A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter"
-
Jun
-
S. Y. Chuan and T. Sculley, "A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter," IEEE J. Solid-State Circuits, vol. 37, no. 6, pp. 674-683, Jun. 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, Issue.6
, pp. 674-683
-
-
Chuan, S.Y.1
Sculley, T.2
-
3
-
-
0036912842
-
"A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration"
-
Dec
-
S. M. Jamal and D. Fu, "A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration," IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1618-1627, Dec. 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, Issue.12
, pp. 1618-1627
-
-
Jamal, S.M.1
Fu, D.2
-
5
-
-
0025568946
-
"A fast-settling CMOS Op Amp for SC circuits with 90-dB dc gain"
-
Dec
-
K. Bult and G. Geelen, "A fast-settling CMOS Op Amp for SC circuits with 90-dB dc gain," IEEE J. Solid-State Circuits, vol. 25, no. 12, pp. 1379-1384, Dec. 1990.
-
(1990)
IEEE J. Solid-State Circuits
, vol.25
, Issue.12
, pp. 1379-1384
-
-
Bult, K.1
Geelen, G.2
-
6
-
-
0018727884
-
"Improvement of the gain MOS amplifiers"
-
Dec
-
B. J. Hosticka, "Improvement of the gain MOS amplifiers," IEEE J. Solid-State Circuits, vol. 14, no. 12, pp. 1111-1114, Dec. 1979.
-
(1979)
IEEE J. Solid-State Circuits
, vol.14
, Issue.12
, pp. 1111-1114
-
-
Hosticka, B.J.1
-
7
-
-
0016333057
-
"Relationship between frequency response and settling time of operational amplifiers"
-
Dec
-
B. Y. Kamath, R. G. Meyer, and P. R. Gray, "Relationship between frequency response and settling time of operational amplifiers," IEEE J. Solid-State Circuits, vol. SC-9, no. 12, pp. 347-352, Dec. 1974.
-
(1974)
IEEE J. Solid-State Circuits
, vol.SC-9
, Issue.12
, pp. 347-352
-
-
Kamath, B.Y.1
Meyer, R.G.2
Gray, P.R.3
-
8
-
-
0031191440
-
"Improved synthesis of gain-boosted regulated-Cascode CMOS stages using symbolic analysis and gm/ID methodology"
-
Jul
-
D. Fandre and A. Viviani, "Improved synthesis of gain-boosted regulated-Cascode CMOS stages using symbolic analysis and gm/ID methodology," IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 1006-1012, Jul. 1997.
-
(1997)
IEEE J. Solid-State Circuits
, vol.32
, Issue.7
, pp. 1006-1012
-
-
Fandre, D.1
Viviani, A.2
-
9
-
-
0036489978
-
"Improved design criteria of gain-boosted CMOS OTA with high-speed optimizations"
-
Mar
-
M. Das, "Improved design criteria of gain-boosted CMOS OTA with high-speed optimizations," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 49, no. 3, pp. 204-297, Mar. 2002.
-
(2002)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process
, vol.49
, Issue.3
, pp. 204-297
-
-
Das, M.1
-
12
-
-
0023600337
-
"IDAC: An interactive design tool for analog CMOS circuits"
-
Dec
-
M. Degranwe et al., "IDAC: An interactive design tool for analog CMOS circuits," IEEE J. Solid-State Circuits, vol. SC-22, no. 12, pp. 1106-1116, Dec. 1987.
-
(1987)
IEEE J. Solid-State Circuits
, vol.SC-22
, Issue.12
, pp. 1106-1116
-
-
Degranwe, M.1
-
13
-
-
0024908745
-
"OASYS: A framework for analog circuit synthesis"
-
Dec
-
R. Harjani, R. Rutenbar, and L. Carley, "OASYS: A framework for analog circuit synthesis," IEEE Trans Computer Aided Des. Integr. Circuits Syst., vol. 8, no. 12, pp. 1247-1266, Dec. 1989.
-
(1989)
IEEE Trans. Computer Aided Des. Integr. Circuits Syst.
, vol.8
, Issue.12
, pp. 1247-1266
-
-
Harjani, R.1
Rutenbar, R.2
Carley, L.3
-
14
-
-
0025383839
-
"OPASYN: A compiler for CMOS operational amplifiers"
-
Feb
-
H. Koh, C. Sequin, and P. Gray, "OPASYN: A compiler for CMOS operational amplifiers," IEEE Trans Computer Aided Des. Integr. Circuits Syst., vol. 9, no. 2, pp. 113-125, Feb. 1990.
-
(1990)
IEEE Trans. Computer Aided Des. Integr. Circuits Syst.
, vol.9
, Issue.2
, pp. 113-125
-
-
Koh, H.1
Sequin, C.2
Gray, P.3
-
15
-
-
0023994941
-
"DELIGHT.SPICE: An optimization-based system for the design of integrated circuits"
-
Apr
-
W. Nye et al., "DELIGHT.SPICE: An optimization-based system for the design of integrated circuits," IEEE Trans Computer Aided Des. Integr. Circuits Syst., vol. 7, no. 4, pp. 501-518, Apr. 1988.
-
(1988)
IEEE Trans. Computer Aided Des. Integr. Circuits Syst.
, vol.7
, Issue.4
, pp. 501-518
-
-
Nye, W.1
-
16
-
-
0030107342
-
"Synthesis of high-performance analog circuits in ASTRX/OBLX"
-
Mar
-
E. Ochotta and L. Carley, "Synthesis of high-performance analog circuits in ASTRX/OBLX," IEEE Trans Computer Aided Des. Integr. Circuits Syst., vol. 15, no. 3, pp. 273-294, Mar. 1996.
-
(1996)
IEEE Trans. Computer Aided Des. Integr. Circuits Syst.
, vol.15
, Issue.3
, pp. 273-294
-
-
Ochotta, E.1
Carley, L.2
-
17
-
-
0028699239
-
"A statistical optimization-based approach for automated sizing of analog cells"
-
F. Medeiro et al., "A statistical optimization-based approach for automated sizing of analog cells," Proc. IEEE ICCAD, pp. 594-597, 1994.
-
(1994)
Proc. IEEE ICCAD
, pp. 594-597
-
-
Medeiro, F.1
-
18
-
-
0024480849
-
"Simulated annealing algorithms: An overview"
-
Jan
-
R. Rutenbar, "Simulated annealing algorithms: An overview," IEEE Circuits Dev. Mag., vol. 5, no. 1, pp. 19-26, Jan. 1989.
-
(1989)
IEEE Circuits Dev. Mag.
, vol.5
, Issue.1
, pp. 19-26
-
-
Rutenbar, R.1
|